MT8926 Zarlink Semiconductor, MT8926 Datasheet - Page 6

• Manufacturer Part Number: MT8926
• Description: T1 Performance Monitoring Adjunct Circuit (PMAC)
• Manufacturer: Zarlink Semiconductor

SEMICMF.019
Data Sheet
1.0
The MT8926 Performance Monitoring Adjunct Circuit (PMAC) is designed to enable a MT8976/77 based T1
interface to gather performance data and perform maintenance functions as per ANSI T1.403 and T1.408.
Performance data collection includes CRC errors, severely errored framing events, frame synchronization-bit
errors, line code violations, and controlled slips. Maintenance functions include the detection of alarms, SF line
loopback code generation and detection, ESF payload loopback, as well as the transport of bit-oriented and
message-oriented signals over the Facility Data Link (FDL).
The control and status data of the MT8926 is transported over spare channels of the existing MT8976/77 ST-BUS
streams. Therefore, no new ST-BUS streams are required to upgrade with the PMAC.
The PMAC has an on-board framer that uses the received signal and extracted 8 kHz clock to achieve
synchronization. The result of this frame alignment is logically ANDed with the SYN bit of the MT8976/77 CSTo
stream to give FECV (see Table 5 on page 10). This will ensure that the PMAC can only declare synchronization
after the framer is synchronized. The MT8926 will align to SF or ESF framing without user selection.
An interrupt (IRQ output) system is also provided to reduce the requirement to monitor ST-BUS channels
continuously for exception conditions. Interrupt sources are divided into group one (G1) for service affecting events
and group two (G2) for counter overflows.
A timer has been included to allow scheduling of T1.403/408 message-oriented performance reports for
transmission over the facility data link. This timer provides a two second output (register accessed) and a one
second output pin.
Two eight bit counters with overflow bits and resets (resets counter and overflow bit) are provided to record line
code violations (BPV) and CRC errors. The BPV counter will not count B8ZS encoding violations. When either
overflow bit goes high it will generate a group two (G2) interrupt.
Two four bit counters are used to record framing error events (FE) and severely errored framing events (SE). The
FE counter has an overflow indication bit and can be cleared (resets counter and overflow bit) by the user. Its
overflow bit will generate a group two (G2) interrupt when it goes high. A G2 interrupt will also be issued whenever
the SE counter is incremented.
The alarms that the PMAC monitors are alternate SF yellow alarm (i.e., twelfth SF framing bit =1, ALRM), ESF
facility data link yellow alarm (RAI), loss of signal (i.e., reception of 128 or more consecutive zeros), and alarm
indication signal (AIS, blue alarm or all ones alarm). Therefore, the MT8926/MT8976/77 combination supports a
comprehensive alarm package.
The PMAC alarm registers and counters are updated as the corresponding events occur. Once per frame (8000
PCCW = Per Channel Control Word
CSTi1
T1
Functional Description
PCCW
0-2
1-3
2
Bit
Transmit Bit-Oriented
Message Register
7
0
3
X
Transmitted First
Transmitted Last
PCCW
Function
4-6
4-6
Figure 3 - CSTi1 Channel Allocation Versus T1 Channels
2
BOM
Tx
7
PCCW
8-10
7-9
2
PMAC Control Word
Bit
7
6
5
4
3
2
1
0
PC
11
W
Function
SER
FER
CRCR
BPVR
FSel
8KEn
INTA
FDLEn
PCCW
12-14
10-12
2
LC
15
W
PCCW
16-18
13-15
Bit 1
2
0
0
1
1
Bit 0
19
X
0
1
0
1
Loopback Control
PCCW
20-22
16-18
2
Word
Normal
Payload Loopback
Line Loopback Enable Code (00001)
Line Loopback Disable Code (001)
Function
23
X
PCCW
24-26
19-21
2
27
X
MT8926
PCCW
28-30
22-24
2
31
X
5