MPC860 Motorola, MPC860 Datasheet - Page 58

• Manufacturer Part Number: MPC860
• Description: Family Hardware Specifications
• Manufacturer: Motorola

Ethernet Electrical Specifications
1
2
58
Num
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater or equal to 2/1.
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
134
135
136
137
138
139
RENA(CD1)
CLSN(CTS1)
TENA inactive delay (from TCLK1 rising edge)
RSTRT active delay (from TCLK1 falling edge)
RSTRT inactive delay (from TCLK1 falling edge)
REJECT width low
CLKO1 low to SDACK asserted
CLKO1 low to SDACK negated
RCLK1
(Input)
(Input)
RxD1
(Input)
Figure 11-57. Ethernet Collision Timing Diagram
Figure 11-58. Ethernet Receive Timing Diagram
Table 11-20. Ethernet Timing (continued)
MPC860 Family Hardware Specifications
Characteristic
2
2
121
124
120
125
121
126
Min
10
10
10
All Frequencies
—
—
1
123
Last Bit
127
Max
20
20
50
50
50
—
MOTOROLA
Unit
CLK
ns
ns
ns
ns
ns