MPC93R52 Motorola, MPC93R52 Datasheet - Page 8

• Manufacturer Part Number: MPC93R52
• Description: LOW VOLTAGE 3.3V LVCMOS 1:11 CLOCK GENERATOR
• Manufacturer: Motorola

MPC93R52
Power Supply Filtering
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Random noise on the V CCA (PLL) power supply impacts the
device characteristics, for instance I/O jitter. The MPC93R52
provides separate power supplies for the output buffers (V CC )
and the phase-locked loop (V CCA ) of the device. The purpose
of this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it is
more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the V CCA
pin for the MPC93R52. Figure 7. illustrates a typical power
supply filter scheme. The MPC93R52 frequency and phase
stability is most susceptible to noise with spectral content in
the 100kHz to 20MHz range. Therefore the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop
across the series filter resistor R F . From the data sheet the
I CCA current (the current sourced through the V CCA pin) is
typically 3 mA (5 mA maximum), assuming that a minimum of
2.98V must be maintained on the V CCA pin. The resistor R F
shown in Figure 7. “V CCA Power Supply Filter” should have a
resistance of 5–25
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 7. “V CCA Power Supply Filter”, the filter
cut-off frequency is around 3-5 kHz and the noise attenuation
at 100 kHz is better than 42 dB.
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC93R52 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
MOTOROLA
The MPC93R52 is a mixed analog/digital product. Its
The minimum values for R F and the filter capacitor C F are
As the noise frequency crosses the series resonant point
VCC
R F = 5–25
Figure 7. V CCA Power Supply Filter
W
R F
to meet the voltage drop criteria.
C F
C F = 22 F
33...100 nF
10 nF
VCCA
VCC
MPC93R52
8
Using the MPC93R52 in zero–delay applications
MPC93R52. Designs using the MPC93R52 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC93R52 clock driver allows for its use as a zero delay
buffer. One example configuration is to use a 4 output as a
feedback to the PLL and configuring all other outputs to a
divide-by-4 mode. The propagation delay through the device
is virtually eliminated. The PLL aligns the feedback clock
output edge with the clock input reference edge resulting a
near zero delay through the device. The maximum insertion
delay of the device in zero-delay applications is measured
between the reference clock input and any output. This
effective delay consists of the static phase offset, I/O jitter
(phase or long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
Calculation of part-to-part skew
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC93R52 are connected together, the maximum overall
timing uncertainty from the common CCLK input to any
output is:
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 11.
t SK(PP) = t ( ) + t SK(O) + t PD, LINE(FB) + t JIT( )
CCLK Common
Any Q Device 1
Any Q Device 2
Nested clock trees are typical applications for the
The MPC93R52 zero delay buffer supports applications
This maximum timing uncertainty consist of 4
Due to the statistical nature of I/O jitter a RMS value (1
QFB Device 1
QFB Device2
Figure 8. MPC93R52 max. device-to-device skew
Max. skew
t JIT( )
+t SK(O)
–t ( )
+t ( )
t JIT( )
t SK(PP)
TIMING SOLUTIONS
t PD,LINE(FB)
+t SK(O)


s
CF
) is