MPC961C Motorola, MPC961C Datasheet - Page 5

• Manufacturer Part Number: MPC961C
• Description: LOW VOLTAGE ZERO DELAY
• Manufacturer: Motorola

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Power Supply Filtering
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC961C provides separate
power supplies for the output buffers (V CC ) and the
phase–locked loop (V CCA ) of the device. The purpose of this
design technique is to isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the V CCA pin for the MPC961C.
The MPC961C is most susceptible to noise with spectral
content in the 10kHz to 10MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the V CC supply and the V CCA
pin of the MPC961C. From the data sheet the I CCA current
(the current sourced through the V CCA pin) is typically 2mA
(5mA maximum), assuming that a minimum of 2.375V (V CC =
3.3V or V CC = 2.5V) must be maintained on the V CCA pin.
The resistor R F shown in Figure 3. must have a resistance of
270
voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20kHz. As the noise
frequency crosses the series resonant point of an individual
capacitor it’s overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL.
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
TIMING SOLUTIONS
DL207 — Rev 0
The MPC961C is a mixed analog/digital product and as
Figure 3. illustrates a typical power supply filter scheme.
Although the MPC961C has several design features to
(V CC = 3.3V) or 5 to 15
VCC
Figure 3. Power Supply Filter
R F = 270 for V CC = 3.3V
R F = 5–15 for V CC = 2.5V
R F
22 F
33...100 nF
(V CC = 2.5V) to meet the
10 nF
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC961C
VCCA
VCC
Go to: www.freescale.com
5
adequate to eliminate power supply noise related problems
in most designs.
Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 15
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091.
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
level of DC current and thus only a single terminated line can
be driven by each output of the MPC961C clock driver. For
the series terminated case however there is no DC current
draw, thus the outputs can drive multiple series terminated
lines. Figure 4. illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC961C clock
driver is effectively doubled due to its capability to drive
multiple lines.
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC961C output buffer is
more than sufficient to drive 50
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC961C. The output
waveform in Figure 5. shows a step in the waveform, this
step is caused by the impedance mismatch seen looking into
the driver. The parallel combination of the 36 series resistor
plus the output impedance does not match the parallel
IN
IN
The MPC961C clock driver was designed to drive high
In most high performance clock networks point–to–point
The waveform plots of Figure 5. show the simulation
Figure 4. Single versus Dual Transmission Lines
resistance to VCC/2. This technique draws a fairly high
OUTPUT
OUTPUT
BUFFER
MPC961
BUFFER
MPC961
14
14
R S = 36
R S = 36
R S = 36
transmission lines on the
Z O = 50
Z O = 50
Z O = 50
MPC961C
MOTOROLA
OutA
OutB0
OutB1
the