MPC961C Motorola, MPC961C Datasheet - Page 6

• Manufacturer Part Number: MPC961C
• Description: LOW VOLTAGE ZERO DELAY
• Manufacturer: Motorola

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MPC961C
combination of the line impedances. The voltage wave
launched down the two lines will equal:
unity reflection coefficient, to 2.62V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 6. should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
MOTOROLA
At the load end the voltage will double, due to the near
Since this step is well above the threshold region it will not
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50 || 50
Rs = 36 || 36
Ro = 14
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
3.0
2.5
2.0
1.5
1.0
0.5
0
= 1.31V
Figure 6. Optimized Dual Line Termination
Figure 5. Single versus Dual Waveforms
OUTPUT
BUFFER
MPC961
14
t D = 3.8956
2
In
OutA
14 + 22
4
R S = 22
R S = 22
25 = 25
k
6
22 = 50
TIME (nS)
t D = 3.9386
OutB
8
Freescale Semiconductor, Inc.
Z O = 50
Z O = 50
For More Information On This Product,
k
10
50
12
Go to: www.freescale.com
14
6
for engineers who want to simulate their specific interconnect
schemes.
Using the MPC961C in zero-delay applications
MPC961C. Designs using the MPC961C as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC961C clock driver allows for its use as a zero delay
buffer. By using the QFB output as a feedback to the PLL the
propagation delay through the device is virtually eliminated.
The PLL aligns the feedback clock output edge with the clock
input reference edge resulting a near zero delay through the
device. The maximum insertion delay of the
zero-delay applications is measured between the reference
clock input and any output. This effective delay consists of
the static phase offset, I/O jitter (phase or long-term jitter),
feedback path delay and the output-to-output skew error
relative to the feedback output.
Calculation of part-to-part skew
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC961C are connected together, the maximum overall
timing uncertainty from the common CCLK input to any
output is:
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
t SK(PP) = t ( ) + t SK(O) + t PD, LINE(FB) + t JIT( )
CCLK Common
Any Q Device 1
Any Q Device 2
SPICE level and IBIS output buffer models are available
Nested clock trees are typical applications for the
The MPC961C zero delay buffer supports applications
This maximum timing uncertainty consist of 4
Due to the statistical nature of I/O jitter a rms value (1 s ) is
QFB Device 1
QFB Device2
Figure 7. MPC961C max. device-to-device skew
Max. skew
t JIT( )
+t SK(O)
–t ( )
+t ( )
t JIT( )
t SK(PP)
TIMING SOLUTIONS
t PD,LINE(FB)
+t SK(O)
DL207 — Rev 0
device in


CF