ADC1210S NXP Semiconductors, ADC1210S Datasheet - Page 10

• Manufacturer Part Number: ADC1210S
• Description: Single 12-bit ADC
• Manufacturer: NXP Semiconductors

Table 8.
[1]
[2]
[3]
Symbol
Clock timing input: pins CLKP and CLKM
f
t
δ
t
t
CMOS mode timing output: pins D11 to D0 and DAV
t
t
t
t
t
LVDS DDR mode timing output: pins D11P to D0P, D11M to D0M, DAVP and DAVM
t
t
t
t
t
clk
lat(data)
d(s)
wake
PD
su
h
r
f
PD
su
h
r
f
clk
Typical values measured at V
at V
Measured between 20 % to 80 % of V
Rise time measured from −50 mV to +50 mV; fall time measured from +50 mV to −50 mV.
DDA
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Parameter
clock frequency
data latency time
clock duty cycle
sampling delay
time
wake-up time
propagation delay
set-up time
hold time
rise time
fall time
propagation delay
set-up time
hold time
rise time
fall time
= 3 V, V
Clock and digital output timing characteristics
10.2 Clock and digital output timing
DDO
[2]
[3]
[2]
[3]
= 1.8 V; V
DDA
INP
Conditions
clock cycles
DCS_EN = 1
DCS_EN = 0
DATA
DAV
DATA
DAV
DATA
DATA
DAV
DATA
DAV
DATA
= 3 V, V
− V
INM
DDO
= −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
DDO
.
= 1.8 V, T
20
-
30
45
-
-
-
-
-
-
0.5
0.5
0.5
-
-
-
-
0.5
0.5
0.5
Min
amb
ADC1210S065
= 25 °C and C
50
50
0.8
<tbd>
3.9
4.2
6.7
-
-
-
3.9
4.2
2.0
-
-
-
7.7
5.1
Typ
14
[1]
-
65
-
70
55
-
-
-
-
-
-
2.4
2.4
2.4
-
-
-
-
2.4
2.4
2.4
Max
L
= 5 pF; minimum and maximum values are across the full temperature range T
60
-
30
45
-
-
-
-
-
0.5
0.5
-
-
-
0.5
0.5
-
0.5
-
0.5
Min
ADC1210S080
50
50
0.8
<tbd>
3.9
4.2
6.5
5.5
-
-
-
3.9
4.2
3.5
2.0
-
-
-
Typ
14
-
80
-
70
55
-
-
-
-
-
-
2.4
2.4
2.4
-
-
-
-
2.4
2.4
2.4
Max
75
-
30
45
-
-
-
-
-
-
0.5
0.5
0.5
-
-
-
-
0.5
0.5
0.5
Min
ADC1210S105
50
50
0.8
<tbd>
3.9
4.2
4.7
3.8
-
-
-
3.9
4.2
2.1
2.0
-
-
-
Typ
14
-
105
-
70
55
-
-
-
-
-
-
2.4
2.4
2.4
-
-
-
-
2.4
2.4
2.4
Max
100
-
30
45
-
-
-
-
-
-
0.5
0.5
0.5
-
-
-
-
0.5
0.5
0.5
Min
ADC1210S125
-
14
50
50
0.8
<tbd>
3.9
4.2
4.3
3.5
-
-
-
3.9
4.2
1.4
2.0
-
-
-
Typ
amb
= −40 °C to +85 °C
125
-
70
55
-
-
-
-
-
-
2.4
2.4
2.4
-
-
-
-
2.4
2.4
2.4
Max
Unit
MHz
clock
cycle
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns