ADC1210S NXP Semiconductors, ADC1210S Datasheet - Page 18

• Manufacturer Part Number: ADC1210S
• Description: Single 12-bit ADC
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1210S_SER_1
Preliminary data sheet
11.3.3 Common-mode output voltage (V
11.3.4 Biasing
11.4.1 Drive modes
11.4 Clock input
A 0.1 μF filter capacitor should be connected between pin VCM and ground to ensure a
low-noise common-mode output voltage. When AC-coupled, pin VCM can then be used to
set the common-mode reference for the analog inputs, for instance via a transformer
middle point.
The common-mode input voltage (V
0.5V
The ADC1210S can be driven differentially (SINE, LVPECL or LVDS) with little or no
influence on the dynamic performances. It can also be driven by a single-ended LVCMOS
signal connected to pin CLKP (CLKM should be connected to ground via a capacitor) or
CLKM (CLKP should be connected to ground via a capacitor).
Fig 17. Equivalent schematic of the common-mode reference circuit
Fig 18. LVCMOS single-ended clock input
DDA
a. Rising edge LVCMOS
for optimal performance and should always be between 0.9 V and 2 V.
0.1 μF
clock input
1.5 V
LVCMOS
VCM
All information provided in this document is subject to legal disclaimers.
PACKAGE
Rev. 01 — 9 April 2010
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CLKM
CLKP
ADC1210S series; CMOS or LVDS DDR digital outputs
ESD
I(cm)
PARASITICS
O(cm)
) on pins INP and INM should be set externally to
)
b. Falling edge LVCMOS
ADC1210S series
COMMON MODE
REFERENCE
clock input
LVCMOS
ADC CORE
© NXP B.V. 2010. All rights reserved.
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CLKM
CLKP
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