TS68020 ATMEL Corporation, TS68020 Datasheet - Page 12

no-image

TS68020

Manufacturer Part Number
TS68020
Description
Hcmos 32-bit Virtual Memory Mpu, 16/20/25 MHZ
Manufacturer
ATMEL Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TS68020DESC02XA 5962-8603202XA
Manufacturer:
TI
Quantity:
15
Part Number:
TS68020MF1-16
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
TS68020MF1-20
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
TS68020MF16
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
TS68020MF1B/C20
Manufacturer:
ATMEL
Quantity:
2
Part Number:
TS68020MF1D/T16
Manufacturer:
AT/WN
Quantity:
2
Part Number:
TS68020MF20
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
TS68020MF25
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
TS68020MFB/C20
Manufacturer:
ATMEL
Quantity:
1
Part Number:
TS68020MFB/C20 5962-8603203YC
Manufacturer:
a
Quantity:
1
Table 6. Dynamic Electrical Characteristics (Continued)
12
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DVSA
DICL
BELCL
SNDN
SNDI
SNDIZ
DADI
DADV
HRrf
CLBA
CLBN
BRAGA
GAGN
GABRN
GN
GA
CHDAR
CLDNR
CLDAW
CHDNW
RADA
DA
RWA
AIST
AIHT
DABA
DOCH
BNHN
TS68020
Parameter
Data Out Valid to DS Asserted (Write)
26
Data in Valid to Clock Low (Data Setup)
Late BERR/HALT Asserted to Clock
Low Setup Time
AS, DS Negated to
DSACKx/BERR/HALT/AVEC Negated
DS Negated to Data On Invalid (Data in
Hold Time)
DS Negated to Data in High Impedance
DSACKx Asserted to Data In Valid
DSACK Asserted to DSACKx Valid
(DSACK Asserted Skew)
RESET Input Transition Time
Clock Low to BG Asserted
Clock Low to BG Negated
BR Asserted to BG Asserted (RMC Not
Asserted)
BGACK Asserted to BG Negated
BGACK Asserted to BR Negated
BG Width Negated
BG Width Asserted
Clock High to DBEN Asserted (Read)
Clock Low to DBEN Negated (Read)
Clock Low to DBEN Negated (Read)
Clock High to DBEN Asserted (Read)
R/W Low to DBEN Asserted (Write)
DBEN Width Asserted
R/W Width Asserted (Write or Read)
Asynchronous Input Setup Time
Asynchronous Input Hold Time
DSACKx Asserted to BERR/HALT
Asserted
Data Out Hold from Clock High
BERR Negated to HALT Negated
(Rerun)
READ
WRITE
Number
Interval
27A
29A
31A
37A
39A
47A
47B
26
27
28
29
31
32
33
34
35
37
39
40
41
42
43
44
45
46
48
53
Min
120
150
1.5
1.5
15
20
90
90
15
60
15
5
0
0
0
0
0
0
0
0
0
5
0
0
68020-16
Max
1.5
3.5
3.5
1.5
80
60
50
15
30
30
30
30
30
30
30
Min
100
125
1.5
1.5
10
15
75
75
50
10
15
68020-20
5
0
0
0
0
0
0
0
0
0
5
0
0
Max
3.5
1.5
3.5
1.5
65
43
10
20
50
25
25
25
25
25
25
Min
100
1.5
1.5
10
60
60
40
80
10
10
5
5
0
0
0
0
0
0
0
0
0
5
0
0
68020-25
Max
1.5
3.5
3.5
1.5
50
40
32
10
20
20
20
20
20
20
18
Clks
Clks
Clks
Clks
Unit
2115A–HIREL–07/02
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(2)(11)
(3)(11)
(4)(11)
(11)
(11)
(11)
(11)
(11)
(11)
(6)
(6)
(6)
(5)
(5)

Related parts for TS68020