TS80C32X2 ATMEL Corporation, TS80C32X2 Datasheet
TS80C32X2
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TS80C32X2 Summary of contents
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CMOS Microcontroller ROMless 1. Description TS80C31X2 is high performance CMOS and ROMless versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C31X2 retains all features of the TSC80C31 with 128 bytes of internal RAM, a 5-source, 4 priority ...
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TS80C31X2 3. Block Diagram XTAL1 XTAL2 ALE/ PROG PSEN CPU EA ( (1) (1) RAM EUART 128x8 C51 CORE IB-bus Timer 0 INT Parallel I/O Ports & Ext. Bus Timer 1 Ctrl Port 0 Port 1 ...
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SFR Mapping The Special Function Registers (SFRs) of the TS80C31X2 fall into the following categories: C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 I/O port registers: P0, P1, P2, P3 Timer registers: TCON, TH0, TH1, TMOD, TL0, ...
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TS80C31X2 5. Pin Configuration P1 P1.1 / T2EX 2 38 P1 P1.7 RST 9 32 P3.0/RxD 10 31 PDIL/ P3.1/TxD ...
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Table 2. Pin Description for 40/44 pin packages PIN NUMBER MNEMONIC DIL LCC VQFP 1 Vss1 P0.0-P0.7 39-32 43-36 37-30 P1.0-P1.7 1-8 2-9 40-44 1-3 P2.0-P2.7 21-28 24-31 ...
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TS80C31X2 6. TS80C31X2 Enhanced Features In comparison to the original 80C31, the TS80C31X2 implements some new features, which are The X2 option. The Dual Data Pointer. The 4 level interrupt priority system. The power-off flag. The ONCE mode. Enhanced UART ...
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XTAL1 XTAL1:2 X2 bit CPU clock STD Mode The X2 bit in the CKCON register (See Table 3.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is ...
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TS80C31X2 CKCON - Clock Control Register (8Fh Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit ...
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Dual Data Pointer Register Ddptr The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify ...
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TS80C31X2 Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this ...
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ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV ...
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TS80C31X2 6.3 TS80C31X2 Serial I/O Port The serial I/O port in the TS80C31X2 is compatible with the serial I/O port in the 80C31. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter ...
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Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, ...
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TS80C31X2 6.3.3 Given Address Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide ...
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Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that ...
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TS80C31X2 SCON - Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit Set by hardware when an ...
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PCON - Power Control Register (87h SMOD1 SMOD0 Bit Bit Number Mnemonic Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode Serial port Mode bit 0 6 SMOD0 ...
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TS80C31X2 6.4 Interrupt System The TS80C31X2 has a total of 5 interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (timers 0 and 1) and the serial port interrupt. These interrupts are shown in Figure 7. INT0 IE0 ...
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IPH low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority ...
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TS80C31X2 IP - Interrupt Priority Register (B8h Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit ...
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IPH - Interrupt Priority High Register (B7h Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit ...
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TS80C31X2 6.5 Idle mode An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to ...
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Table 11. The state of ports during idle and power-down modes Program Mode ALE Memory Idle External Power Down External Rev January, 2001 PSEN PORT0 1 1 Floating 0 0 Floating TS80C31X2 PORT1 PORT2 PORT3 Port Data ...
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TS80C31X2 TM 6.7 ONCE Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using TS80C31X2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C31X2; the following ...
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Power-Off Flag The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by V the device and could be generated for example by ...
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TS80C31X2 7. Electrical Characteristics 7.1 Absolute Maximum Ratings Ambiant Temperature Under Bias commercial I = industrial Storage Temperature Voltage Voltage Voltage on Any Pin to V ...
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DC Parameters for Standard Voltage + - + Table 14. DC Parameters in Standard ...
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TS80C31X2 Symbol Parameter I Power Supply Current Maximum values (7) mode: operating I Power Supply Current Maximum values (7) mode: idle 7.4 DC Parameters for Low Voltage + ...
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Symbol Parameter I Power Supply Current Maximum values (7) mode: idle NOTES 1. I under reset is measured with all output pins disconnected; XTAL1 driven with 0.5V; XTAL2 N.C RST ...
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TS80C31X2 Reset = Vss after a high pulse during at least 24 clock cycles Reset = Vss after a high pulse during at least 24 clock cycles Figure 11. I Reset = Vss after a high pulse during at least ...
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AC Parameters 7.5.1 Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or ...
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TS80C31X2 7.5.2 External Program Memory Characteristics Symbol T Oscillator clock period T ALE pulse width LHLL T Address Valid to ALE AVLL T Address Hold After ALE LLAX T ALE to Valid Instruction In LLIV T ALE to PSEN LLPL ...
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Table 20. AC Parameters for a Variable Clock: derating formula Symbol Type Standard Clock T Min LHLL T Min AVLL T Min LLAX T Max LLIV ...
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TS80C31X2 7.5.4 External Data Memory Characteristics Symbol T RD Pulse Width RLRH T WR Pulse Width WLWH Valid Data In RLDV T Data Hold After RD RHDX T Data Float After RD RHDZ T ALE to Valid ...
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Table 22. AC Parameters for a Fix Clock Speed -M 40 MHz Symbol Min Max T 130 RLRH T 130 WLWH T 100 RLDV T 0 RHDX T 30 RHDZ T 160 LLDV T 165 AVDV T 50 100 LLWL ...
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TS80C31X2 Table 23. AC Parameters for a Variable Clock: derating formula Symbol Type Standard Clock T Min RLRH T Min WLWH T Max RLDV T Min x RHDX ...
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External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Figure 16. External Data Memory Read Cycle 7.5.7 Serial Port Timing - Shift Register Mode Symbol T XLXL T QVHX T XHQX T XHDX ...
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TS80C31X2 Table 26. AC Parameters for a Variable Clock: derating formula Symbol Type Standard Clock T Min 12 T XLXL T Min QVHX T Min XHQX T Min x XHDX T Max ...
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External Clock Drive Characteristics (XTAL1) Symbol Parameter T Oscillator Period CLCL T High Time CHCX T Low Time CLCX T Rise Time CLCH T Fall Time CHCL T /T Cyclic ratio in X2 mode CHCX CLCX 7.5.10 External Clock ...
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TS80C31X2 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V 7.5.13 Clock Waveforms Valid in normal clock ...
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Ordering Information TS 80C31X2 -M: VCC: 5V +/- 10% 40 MHz, standard mode 20 MHz, X2 mode -V: VCC: 5V +/- 10% 40 MHz, standard mode 30 MHz, X2 mode -L: VCC: 2 MHz, standard ...
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TS80C31X2 TS80C31X2 ROMless -MCA X -MCB X -MCC X -MCE X -VCA X -VCB X -VCC X -VCE X -LCA X -LCB X -LCC X -LCE X -MIA X -MIB X -MIC X -MIE X -VIA X -VIB X -VIC ...