TS83102G0B ATMEL Corporation, TS83102G0B Datasheet - Page 38

• Manufacturer Part Number: TS83102G0B
• Description: 10-bit 2 GSPS ADCthis State-of-the-art 10-bit 2 GSPS Converter Offers an Unprecedented Bandwidth of 3.3 GHZ And Excellent Band Flatness, Allowing to Directly Digitize Very High if Signals (2nd And 3rd Nyquist Zones) With High Linearity : The SFDR Rem
• Manufacturer: ATMEL Corporation

Principle of Data Ready Signal Control by DRRB Input Command
Data Ready Output
Signal Reset
Data Ready Output
Signal Restart
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TS83102G0B
When used with Atmel’s TS81102G0 1:4/8 8/10 bit DMUX, it is not necessary to initialize Data
Ready, as this device can start on either clock edge.
The Data Ready signal is reset on the DRRB input command’s falling edge, on the ECL logical
low level (-1.8V). DRRB may also be tied to V
ter reset. As long as DRRB remains at a logical low level, (or tied to V
Ready output remains at a logical zero and is independent of the external free-running encod-
ing clock.
The Data Ready output signal (DR/DRB) is reset to a logical zero after TRDR.
TRDR is measured between the -1.3V point of the DRRB input command’s falling edge and
the zero crossing point of the differential Data Ready output signal (DR/DRB).The Data Ready
Reset command may be a pulse of 1 ns minimum time width.
The Data Ready output signal restarts on the DRRB command’s rising edge, on the ECL logi-
cal high level (-0.8V).
DRRB may also be grounded, or may float, for normal free-running of the Data Ready output
signal. The Data Ready signal’s restart sequence depends on the logical level of the external
encoding clock, at a DRRB rising edge instant:
•
•
Consequently, as the analog input is sampled on the clock’s rising edge, the first digitized data
corresponding to the first acquisition (N), after a Data Ready signal restart (rising edge), is
always strobed by the third rising edge of the Data Ready signal.
The time delay (TD1) is specified between the last point of a change in the differential output
data (zero crossing point) to the rising or falling edge of the differential Data Ready signal
(DR/DRB) [zero crossing point].
Note:
The DRRB’s rising edge occurs when the external encoding clock input (CLK/CLKB) is
LOW : the Data Ready output’s first rising edge occurs after half a clock period on the
clock’s falling edge, and a TDR delay time of 410 ps, as defined above.
The DRRB’s rising edge occurs when the external encoding clock input (CLK/CLKB) is
HIGH : the Data Ready output’s first rising edge occurs after one clock period on the
clock’s falling edge, and a TDR delay time of 410 ps.
For normal initialization of the Data Ready output signal, the external encoding clock signal fre-
quency and level must be controlled. The minimum encoding clock sampling rate for the ADC is
150 Msps, due to the internal Sample and Hold drop rate. Consequently the clock cannot be
stopped.
EE
= - 5V for the Data Ready output signal mas-
EE
= - 5V), the Data
2101C–BDC–02/04