TS83102G0B ATMEL Corporation, TS83102G0B Datasheet - Page 42

• Manufacturer Part Number: TS83102G0B
• Description: 10-bit 2 GSPS ADCthis State-of-the-art 10-bit 2 GSPS Converter Offers an Unprecedented Bandwidth of 3.3 GHZ And Excellent Band Flatness, Allowing to Directly Digitize Very High if Signals (2nd And 3rd Nyquist Zones) With High Linearity : The SFDR Rem
• Manufacturer: ATMEL Corporation

Equivalent Single-
ended Clock Input
Voltage Levels (0 dBm
Typical)
Noise Immunity Information
Digital Outputs: Termination and Logic Compatibility
42
TS83102G0B
Figure 45. Single-ended Clock Inputs - Ground Common Mode
The circuit’s noise immunity performance begins at the design level. Efforts have been made
on the design to make the device as insensitive as possible to chip environment perturbations,
which may result from the circuit itself or be induced by external circuitry (cascode stage’s iso-
lation, internal damping resistors, clamps, internal on-chip decoupling capacitors.)
Furthermore, the fully differential operation from the analog input up to the digital output pro-
vides enhanced noise immunity by common mode noise rejection. The common mode noise
voltage induced on the differential analog and clock inputs is cancelled out by these balanced
differential amplifiers.
Moreover, proper active signal shielding has been provided on the chip to reduce the amount
of coupled noise on the active inputs. The analog and clock inputs of the TS83102G0B device
have been surrounded by ground pins, which must be directly connected to the external
ground plane.
Each single-ended output of the TS83102G0B’s differential output buffers are internally 50 Ω
terminated, and feature a 100 Ω differential output impedance. The 50 Ω resistors are con-
nected to the VPLUSD digital power supply. The TS83102G0B output buffers are designed to
drive 50 Ω controlled impedance lines properly terminated by a 50 Ω resistor. A 10.5 mA bias
current flowing alternately into one of the 50 Ω resistors when switching, ensures a 0.25V
single-ended voltage drop across the resistor (0.5V differential).
Each single-ended output transmission line length must be kept identical (< 3 mm). Mis-
matches in the differential line lengths may cause variations in the output differential common
mode.
It is recommended to bypass the midpoint of the differential 100 Ω termination with a 47 pF
capacitor, so as to avoid common mode perturbations in case of a slight mismatch in the dif-
ferential output line lengths.
+0.32
-0.32
V
CLK
CLKB
0V
t
2101C–BDC–02/04