PIC16C745/P Microchip Technology, PIC16C745/P Datasheet - Page 18
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PIC16C745/P
Manufacturer Part Number
PIC16C745/P
Description
8-Bit CMOS Microcontrollers with USB
Manufacturer
Microchip Technology
Datasheet
1.PIC16C745P.pdf
(158 pages)
- Current page: 18 of 158
- Download datasheet (3Mb)
PIC16C745/765
TABLE 4-1:
DS41124A-page 18
Address
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Note 1:
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Bank 1
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from either bank.
4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
TXSTA
SPBRG
ADCON1
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents
are transferred to the upper byte of the program counter.
Name
(3)
(3)
—
—
—
—
—
—
—
—
—
—
—
—
—
(3)
(4)
(4)
(3)
(1,3)
(3)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Register
PORTD Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Baud Rate Generator Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
PSPIE
TRISC7
RBPU
CSRC
Bit 7
GIE
IRP
IBF
—
—
—
—
—
(4)
INTEDG
TRISC8
Bit 6
PEIE
ADIE
OBF
RP1
TX9
—
—
—
—
—
PORTA Data Direction Register
TXEN
T0CS
IBOV
RCIE
Bit 5
T0IE
RP0
—
—
—
—
—
Advanced Information
Write Buffer for the upper 5 bits of the Program Counter
PSPMODE
SYNC
T0SE
INTE
TXIE
Bit 4
TO
—
—
—
—
USBIE
RBIE
Bit 3
PSA
PD
—
—
—
—
—
—
PORTE Data Direction Bits
TRISC2
CCP1IE
PCFG2
BRGH
Bit 2
T0IF
PS2
—
—
Z
TRISC1
TMR2IE
PCFG1
TRMT
Bit 1
INTF
POR
PS1
DC
—
1999 Microchip Technology Inc.
TRISC0
TMR1IE
CCP2IE
PCFG0
TX9D
RBIF
Bit 0
BOR
PS0
C
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
11-- -111 11-- -111
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
---- ---0 ---- ---0
---- --qq ---- --uu
1111 1111 1111 1111
0000 -010 0000 -010
0000 0000 0000 0000
---- -000
Value on:
POR,
BOR
—
—
—
—
—
—
—
—
—
—
—
—
—
other resets
Value on all
---- -000
(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
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