ISL12027 Intersil Corporation, ISL12027 Datasheet - Page 14

• Manufacturer Part Number: ISL12027
• Manufacturer: Intersil Corporation

BSW: Power Control Bit
The Power Control bit, BSW, determines the conditions for
switching between V
options.
Option 1. Standard: Set “BSW = 0”
Option 2. Legacy /Default Mode: Set “BSW = 1”
See Power Control Operation later in this document for more
details. Also see “I
backup and LVR Operation” in the Applications section for
important details.
VTS2, VTS1, VTS0: V
The ISL12027 is shipped with a default V
(V
a non-volatile with no protection, therefore any writes to this
location can change the default value from that marked on
the package. If not changed with a non-volatile write, this
value will not change over normal operating and storage
conditions. However, ISL12027 has four (4) additional
selectable levels to fit the customers application. Levels are:
4.64V (default), 4.38V, 3.09V, 2.92V and 2.63V. The V
selection is via 3 bits (VTS2, VTS1 and VTS0). See Table 5
below.
Device Operation
Writing to the Clock/Control Registers
Changing any of the bits of the clock/control registers
requires the following steps:
Write all eight bytes to the RTC registers, or one byte to the
SR, or one to five bytes to the control registers. This
sequence starts with a start bit, requires a slave byte of
“11011110” and an address within the CCR and is terminated
by a stop bit. A write to the EEPROM registers in the CCR
will initiate a non-volatile write cycle and will take up to 20ms
to complete. A write to the RTC registers (SRAM) will require
much shorter cycle time (t = t
1. Write a 02h to the Status Register to set the Write Enable
2. Write a 06h to the Status Register to set both the Register
RESET
VTS2
Latch (WEL). This is a volatile operation, so there is no
delay after the write. (Operation preceded by a start and
ended with a stop).
Write Enable Latch (RWEL) and the WEL bit. This is also
a volatile cycle. The zeros in the data byte are required.
(Operation proceeded by a start and ended with a stop).
0
0
0
0
1
) per the ordering information table. This register is
VTS1
0
0
1
1
0
2
C Communications During Battery
DD
and Back Up Battery. There are two
RESET
VTS0
TABLE 5.
0
1
0
1
0
BUF
14
). Writes to undefined areas
Select Bits
DD
V
4.64V
4.38V
3.09V
2.92V
2.63V
RESET
threshold
RESET
ISL12027
have no effect. The RWEL bit is reset by the completion of a
write to the CCR, so the sequence must be repeated to
again initiate another change to the CCR contents. If the
sequence is not completed for any reason (by sending an
incorrect number of bits or sending a start instead of a stop,
for example) the RWEL bit is not reset and the device
remains in an active mode. Writing all zeros to the status
register resets both the WEL and RWEL bits. A read
operation occurring between any of the previous operations
will not interrupt the register write operation.
Alarm Operation
Since the alarm works as a comparison between the alarm
registers and the RTC registers, it is ideal for notifying a host
processor of a particular time event and trigger some action
as a result. The host can be notified by polling the Status
Register (SR) Alarm bits. These two volatile bits (AL1 for
Alarm 1 and AL0 for Alarm 0), indicate if an alarm has
happened. The AL1 and AL0 bits in the status register are
reset by the falling edge of the eighth clock of status register
read.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
Power Control Operation
The power control circuit accepts a V
Many types of batteries can be used with Intersil RTC
products. For example, 3.0V or 3.6V Lithium batteries are
appropriate, and battery sizes are available that can power
an Intersil RTC device for up to 10 years. Another option is
to use a SuperCap for applications where V
for up to a month. See the Applications Section for more
information.
1. Single Event Mode is enabled by setting the AL0E or
2. Interrupt Mode (or “Pulsed Interrupt Mode” or PIM) is
AL1E bit to “1”, the IM bit to “0”, and disabling the
frequency output. This mode permits a one-time match
between the alarm registers and the RTC registers. Once
this match occurs, the AL0 or AL1 bit is set to “1”. Once
the AL0 or AL1 bit is read, this will automatically resets it.
Both Alarm registers can be set at the same time to
trigger alarms. Polling the SR will reveal which alarm has
been set.
enabled by setting the AL0E or AL1E bit to “1” the IM bit
to “1”, and disabling the frequency output. If both AL0E
and AL1E bits are set to 1, then only the AL0E PIM alarm
will function (AL0E overrides AL1E). This means that
once the interrupt mode alarm is set, it will continue to
alarm for each occurring match of the alarm and present
time. This mode is convenient for hourly or daily
hardware interrupts in microcontroller applications such
as security cameras or utility meter reading. Interrupt
Mode CANNOT be used for general periodic alarms,
however, since a specific time period cannot be
programmed for interrupt, only matches to a specific time
of day. The interrupt mode is only stopped by disabling
the IM bit or the Alarm Enable bits.
DD
and a V
DD
is interrupted
BAT
April 17, 2006
input.
FN8232.3