T15L256A TM tech, T15L256A Datasheet - Page 7

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T15L256A

Manufacturer Part Number
T15L256A
Description
32K X 8 LOW POWER CMOS STATIC RAM
Manufacturer
TM tech
Datasheet
tm
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
2. The data output from
3.
4. Transition is measured
5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of
should not be applied.
guaranteed but not 100% tested.
t WP or (t WHZ + t DW ) to allow the I/O drivers to turn off and data to be placed on the bus for the
required t DW .
apply and the write pulse can be as short as the specified t WP .
D
CH
OUT
TE
provides the read data for the next address.
If
OE
D
OUT
500 mV from steady state with
is high during a
are the same as the data written to
WE
controlled write cycle, this requirement does not
P. 7
C
L
= 5pF.
D
Publication Date: APR. 2001
IN
This parameter is
during the write cycle.
T15L256A
Revision: C

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