T15N1024A TM tech, T15N1024A Datasheet - Page 7

• Manufacturer Part Number: T15N1024A
• Description: 128K X 8 LOW POWER CMOS STATIC RAM
• Manufacturer: TM tech

TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
READ CYCLE 2
(Chip Enable Controlled)
Notes (READ CYCLE) :
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
4. At any given temperature and voltage condition. t
5. Transition is measured 200mV from steady state voltage with load.
6. Device is continuously selected with
TM Technology Inc. reserves the right
to change products or specifications without notice.
Address
CE1
CE2
V
and from device to device interconnection.
100% tested.
D
HZ
OH
out
D
and t
out
or V
OHZ
OL
CH
TE
Previous Data Vaild
levels.
are defined as the time at which the outputs achieve the open circuit condition referenced to
t
OH
t
AA
CE
t
ACE
t
LZ
1
=V
IL
t
RC
.
HZ
P. 7
(max.) is less than t
Data Vaild
This parameter is sampled and not
LZ
(min.) both for a given device
Publication Date: FEB. 2003
T15N1024A
t
HZ
DON'T CARE
UNDEFINED
DON'T CARE
UNDEFINED
Revision:E