T15V4M08A TM tech, T15V4M08A Datasheet - Page 7

• Manufacturer Part Number: T15V4M08A
• Description: 512K X 8 LOW POWER CMOS STATIC RAM
• Manufacturer: TM tech

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TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled,
READ CYCLE 2 (
Notes : (READ CYCLE) :
1.
2. All read cycle timing is referenced from the last valid address to the fir st transition address.
3. t
4. At any given temperature and voltage condition. t
5. Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not
6. Device is continuously selected with CE =V
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
A d d r e s s
D
V
and from device to device interconnection.
100% tested.
WE
HZ
A d d r e s s
OH
C E
O E
O U T
and t
D O UT
or V
are high for read cycle.
OHZ
OL
CH
TE
levels.
P revious Data Valid
are defined as the time at which the outputs achieve the open circuit condition referenced to
H i g h - Z
CE
WE
=
t OH
=
V
OE
IH
)
t
L Z
=
t AA
V ,
IL
t
t
O L Z
t
A C E
A A
WE
IL
t
O E
=
.
V
HZ
t RC
IH
(max.) is less than t
)
t
R C
P. 7
Data V alid
Preliminary T15V4M08A
LZ
(min.) both for a given device
Publication Date: MAR. 2001
t
O H Z
t
H Z
t
O H
D O N ' T C A R E
U N D E F I N E D
Revision:0.A