AN214 Philips, AN214 Datasheet - Page 13

• Manufacturer Part Number: AN214
• Description: 74F Extended Octal-Plus Family Applications
• Manufacturer: Philips

All parameters are worst-case, unless otherwise specified.
Philips Semiconductors
Table 3. The Extended Octal-Plus Family Capabilities Summary
NOTES:
3-St
OC
Reg
Latch = HIGH logic level on the Latch Enable logic, data passes directly through D-type latch,
**
MR
OE
June 1988
“Light-Load” buffer and Line Driver Functions
74F455/456
74F540/541
74F655A/656A
74F827/828
“Light-Load” Register and Latch Functions
74F821/822
74F823/824
74F825/826
74F841/842
74F843/844
74F845/846
“Light-Load” Transceiver Functions
74F545
74F550/551
74F552
74F588
74F620/623
74F621/622
74F640
74F641/642
74F646A/648A
74F647/649
74F651A/652A
74F653/654
74F657
74F861/862
74F863/864
74F1245
74F2951/2952
74F extended octal-plus family applications
Number
Part
= 3-State
= Open Collector
= LOW-to-HIGH edge clocked D-type register
= These devices utilize standard FAST input structures producing input currents of +20 A and –0.6mA.
= Master Reset
= Output Enable
HIGH-to-LOW logic level transition of the Latch Enable, data is stored in the D-type latch.
10-bit
10-bit
10-bit
10-bit
Bits
8-bit
8-bit
8-bit
9-bit
8-bit
9-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
9-bit
8-bit
8-bit
#
INV/NINV
INV/NINV
INV/NINV
NINV/INV
NINV/INV
NINV/INV
NINV/INV
NINV/INV
NINV/INV
NINV/INV
NINV/INV
INV/NINV
NINV/INV
NINV/INV
NINV/INV
NINV/INV
INV/NINV
NINV/INV
NINV/INV
NINV/INV
INV/NINV
Polarity
NINV
NINV
NINV
NINV
NINV
INV
A
A/B 3-St
A/B 3-St
A/B 3-St
A/B 3-St
A/B 3-St
A/B 3-St
Output
A
B
B
A
B
A
B
B
A
B
B
A
B
A
B
A
B
A
AB OC
A
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
3-St
3-St
3-St
3-St
3-St
3-St
3-St
3-St
3-St
3-St
N
N
N
N
N
= 3-St
3-St
3-St
3-St
3-St
3-St
3-St
3-St
3-St
3-St
3-St
3-St
3-St
3-St
3-St
OC
OC
OC
OC
OC
Broad-
side
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–15/64mA
–15/64mA
–15/64mA
–15/64mA
–15/64mA
–15/64mA
–15/64mA
–15/48mA
–15/48mA
–15/48mA
–3/24mA
–15/64mA
–15/64mA
–3/24mA
–15/64mA
–3/24mA
–3/24mA
–15/64mA
–15/64mA
–3/24mA
OC/64mA
OC/24mA
–15/64mA
OC/64mA
OC/20mA
–15/48mA
OC/64mA
–15/48mA
–15/64mA
OC/64mA
–15/64mA
–3/24mA
–15/64mA
–15/64mA
–15/64mA
–3/24mA
–15/64mA
I
OH
MIN
/I
OL
Storage
B
A
B
A
B
A
2 Reg
2 Reg
2 Reg
2 Reg
None
None
None
None
Latch
Latch
Latch
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
N
N
N
N
N
N
Reg
Reg
Reg
-Reg
-Reg
-Reg
-Reg
-Reg
-Reg
13
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
Speed
10.5ns
10.5ns
10.5ns
10.5ns
13.0ns
12.5ns
13.0ns
12.0ns
19.5ns
20.0ns
10.0ns
10.0ns
12.5ns
11.0ns
11.5ns
11.0ns
7.5ns
7.5ns
7.5ns
9.0ns
7.0ns
7.0ns
7.5ns
7.5ns
7.5ns
7.5ns
7.5ns
8.0ns
8.0ns
8.0ns
8.0ns
Parity
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Multiple/Ctr Pkg. GND Pins,
Broadside pinout of 74F240
Data, MR, OE, & Clock EN Inputs
Data, MR, OE, & Clock EN Inputs
Data, MR, OE, & Clock EN Inputs
Data, MR, OE, & LE Enable Inputs
Data, MR, OE, & LE Enable Inputs
Data, MR, OE, & LE Enable Inputs
A
B
A
B
IEEE-488/GPIB w/line term. resistors
A
B
A
B
A
A
B
A
A
A
A
B
A
B
A
A
A
B
A
E
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
,
O
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
B
B
B
B
B
B
= –15/64mA
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
, ERROR, status registers, 50MHz
, Multiple/Center Pkg. GND pins **
, PARITY, ERROR, status registers
, Multiple/Center Pkg. GND pins **
, B
, A
, PARITY, ERROR = –15/64mA
, Multiple/Center Pkg. GND pins
, “Light-Load” pin-for-pin ’F245 replacement
, registers for A
, registers for A
, registers for A
, registers for A
N
N
port = 85MHz (min.)
port = 45MHz (min.)
Comments
N
N
N
N
& B
& B
& B
& B
E
N
N
N
N
,
ports, 80MHz (min.) **
ports, 80MHz (min.)
ports, 40MHz (min.)
ports, 80MHz (min.)
O
= –15/64mA
Application note
AN214