S-1200 Seiko Instruments, S-1200 Datasheet - Page 13

• Manufacturer Part Number: S-1200
• Description: HIGH RIPPLE-REJECTION LOW DROPOUT LOW INPUT-AND-OUTPUT CAPACITANCE CMOS VOLTAGE REGULATOR
• Manufacturer: Seiko Instruments

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Rev.3.2
Operation
1. Basic operation
2. Output transistor
Figure 12 shows the block diagram of the S-1200 Series.
The error amplifier compares the reference voltage (V
divided by feedback resistors R
to ensure a certain output voltage free of any fluctuations of input voltage and temperature.
The S-1200 Series uses a low on-resistance P-channel MOS FET as the output transistor.
Be sure that V
to inverse current flowing from the VOUT pin through a parasitic diode to the VIN pin.
_00
HIGH RIPPLE-REJECTION LOW DROPOUT LOW INPUT-AND-OUTPUT CAPACITANCE CMOS VOLTAGE REGULATOR
OUT
does not exceed V
*1.
VSS
VIN
Current
supply
Reference voltage
V
Parasitic diode
ref
s
circuit
and R
IN
Seiko Instruments Inc.
f
+ 0.3 V to prevent the voltage regulator from being damaged due
. It supplies the output transistor with the gate voltage necessary
−
+
amplifier
Error
Figure 12
ref
) with V
R
R
s
f
fb
V
*1
, which is the output voltage resistance-
fb
VOUT
S-1200 Series
13