MT28F322D20 Micron Technology, MT28F322D20 Datasheet - Page 27

• Manufacturer Part Number: MT28F322D20
• Description: (MT28F322D18 / MT28F322D20) FLASH MEMORY
• Manufacturer: Micron Technology

ASYNCHRONOUS READ MODE
figuration state. To use the device in an asynchronous-
only application, ADV# and CLK must be tied to V
WAIT# should be floated.
is purely random (
address, the CE# signal needs to go LOW, and the OE#
signal needs to go LOW. In this case the data is placed on
the data bus and the processor is ready to receive the
data.
SYNCHRONOUS BURST READ MODE
rate than is possible with asynchronous read mode. The
rising edge of the clock CLK is used to latch the address
with CE# and ADV# LOW (see timing diagram: Single
Synchronous READ Operation). The burst read configu-
ration is set in the read configuration register, where
frequency, data output, WAIT# signal, burst sequence,
clock, and burst length are configured setting the related
bits.
the following way:
1. In READ operation there is no bank boundary as far as
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
The asynchronous read mode is the default read con-
Toggling the address lines from A0 to A20, the access
The ADV# signal needs to be toggled to latch the
The burst read mode is used to achieve a faster data
All blocks in both banks are burstable.
The BURST READ works across the bank boundary in
burst access is concerned. If, for example, burst starts
in bank a, the application can keep clocking until
bank boundary is reached and then read from bank b.
If the application keeps clocking beyond bank b last
location, then the internal counter restarts from bank
a first address. (See Figure 13.)
t
AA).
SS
and
ASYNC/PAGE/BURST FLASH MEMORY
27
2. If one bank is in program or erase mode and the
3. If burst is started in one bank and the bank boundary
Bank b start address
Bank a start address
Bank b end address
Bank a end address
application starts burst access in that bank, then the
status register data is returned. The internal address
counter is incremented at every clock pulse.
is crossed, and the other bank is in program or erase
mode, then the status register data is returned as the
first location of the bank. If the application keeps
clocking, the internal address counter gets
incremented at every clock cycle. If bank end is
crossed, then data from the other bank is returned as
shown in Figure 13.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Bank Boundary Wrapping
(Bottom Boot Example)
Figure 13
0 00000h
0 7FFFFh
0 80000h
1 FFFFFh
2 MEG x 16
©2002, Micron Technology, Inc.
Bank a
bank boundary
Bank b