MT28F322D20 Micron Technology, MT28F322D20 Datasheet - Page 9

• Manufacturer Part Number: MT28F322D20
• Description: (MT28F322D18 / MT28F322D20) FLASH MEMORY
• Manufacturer: Micron Technology

COMMAND STATE MACHINE (CSM)
chine (CSM) using standard microprocessor write tim-
ings. The CSM acts as an interface between external
microprocessors and the internal write state machine
(WSM). The available commands are listed in Table 3,
their definitions are given in Table 4, and their descrip-
tions in Table 5. Program and erase algorithms are
automated by an on-chip WSM. (For more specific
information about the CSM transition states, see Micron
technical note TN-28-33, “Command State Machine De-
scription and Command Definition.”
the WSM executes the appropriate algorithm, which gen-
erates the necessary timing signals to control the device
internally to accomplish the requested operation. A com-
mand is valid only if the exact sequence of WRITEs is
completed. After the WSM completes its task, the WSM
status bit (SR7) (see Table 7) is set to a logic HIGH level (1),
allowing the CSM to respond to the full command set
again.
OPERATIONS
JEDEC 8-bit command code with conventional micro-
processor timings into an on-chip CSM through I/Os
DQ0–DQ7. The number of bus cycles required to activate
a command is typically one or two. The first operation is
always a WRITE. Control signals CE#, ADV#, and WE#
must be at a logic LOW level (V
must be at logic HIGH (V
needed, can be a WRITE or a READ depending upon the
command. During a READ operation, control signals
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
Commands are issued to the command state ma-
Once a valid PROGRAM/ERASE command is entered,
Device operations are selected by entering a standard
Command State Machine Codes For Device Mode Selection
COMMAND DQ0–DQ7
IH
40h/10h
). The second operation, when
D0h
20h
50h
60h
60h
70h
90h
98h
B0h
C0h
FFh
IL
), and OE# and RST#
CODE ON DEVICE MODE
Program setup/alternate program setup
Block erase setup
Clear status register
Protection configuration setup
Set read configuration register
Read status register
Read protection configuration register
Read query
Program/erase suspend
Protection register program/lock
Program/erase resume – erase confirm
Read array
Table 3
ASYNC/PAGE/BURST FLASH MEMORY
9
CE#, ADV#, and OE# must be at a logic LOW level (V
and WE# and RST# must be at logic HIGH (V
write, read, reset, standby, and output disable.
cuitry initializes the chip to a read array mode of opera-
tion. Changing the mode of operation requires that a
command code be entered into the CSM. For each one of
the two memory partitions, an on-chip status register is
available. These two registers allow the progress of the
various operations that can take place on a memory bank
to be monitored. One of the two status registers is inter-
rogated by entering a READ STATUS REGISTER com-
mand onto the CSM (cycle 1), specifying an address within
the memory partition boundary, and reading the register
data on I/Os DQ0–DQ7 (cycle 2). Status register bits SR0-
SR7 correspond to DQ0–DQ7 (see Table 7).
COMMAND DEFINITION
WSM executes an internal algorithm, generating the nec-
essary timing signals to program, erase, and verify data.
See Table 4 for the CSM command definitions and data
for each of the bus cycles.
STATUS REGISTER
whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored by
toggling OE# and CE# and reading the resulting status
code on I/Os DQ0–DQ7. The high-order I/Os (DQ8–DQ15)
Table 6 illustrates the bus operations for all the modes:
When the device is powered up, internal reset cir-
Once a specific command code has been entered, the
The status register allows the user to determine
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2 MEG x 16
©2002, Micron Technology, Inc.
IH
).
IL
),