MT9171 Mitel Networks, MT9171 Datasheet
MT9171
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MT9171 Summary of contents
Page 1
... Digital PABX line cards and telephone sets • 160 kbit/s single chip modem Description The MT9171 (DSIC) and MT9172 (DNIC) are multi- function devices capable of providing high speed, full duplex digital transmission up to 160 kbit/s over DSTi/Di Transmit Prescrambler ...
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... MT9171/ LOUT 2 21 VBias 20 VRef 3 19 MS2 MS1 MS0 RegC F0/CLD 14 9 CDSTi/CDi 13 10 CDSTo/CDo 12 11 VSS 22 PIN PDIP/CERDIP Pin Description Pin # Name Line Out. Transmit Signal output (Analog). Referenced to V OUT Internal Bias Voltage output. Connect via 0.33 µF decoupling capacitor to V ...
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... When Bias to the precanceller path is enabled and functions normally. An OUT Disable. When held to logic “1”, L OUT functions normally. An internal pulldown ( provided on this OUT Connect MT9171/72 the internal path from L to the ’, OUT is disabled (i.e., output = V ). When Bias 9-135 ...
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... MT9171/ AAAAA A AAAA AAAA A A AAAA DSTi A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AA AAAA A A DSTo AAAA ...
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... Figure 1 shows the block diagram of the MT9171/72. The DNIC provides a bidirectional interface between the DV (data/voice) port and a full duplex line operating 160 kbit/s over a single pair of twisted wires ...
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... MT9171/72 AAAA A AAAA A AAAA A A AAAA A AAAA AAAA A A AAAA A AAAA AAAA A AAAA A AAAA A A AAAA A A AAAA AAAA AAAA A AAAA A AAAA A AAAA A AAAA A A AAAA A A AAAA AAAA AAAA A AAAA A AAAA A A AAAA A A AAAA AAAA AAAA A AAAA A AAAA A AAAA ...
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... Channel Time 16 Figure Port (Modes 2, Figure Port (Modes 1,5) MT9171/ entering the DNIC this signal AAAA AAAA AAAAAAAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAA AAAA AAAA AAAA ...
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... MT9171/72 of the near end signal may be disabled by holding the Precan pin high. This mode simplifies the design of external line transceivers used for loop extension applications. The Precan pin features an internal pull-down which allows this unconnected in applications where this function is not required. The resultant signal passes through a receive filter to bandlimit and equalize it ...
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... F0o/RCK Name Input/Output Input F0o Output RCK Output Input F0o Output Input F0o Output F0o Output RCK Output F0o Output Input F0o Output Table 3. Pin Configurations MT9171/72 C4/TCK Name Input/Output C4 Input TCK Output C4 Input C4 Input C4 Output TCK Output C4 Output C4 Input 9-141 ...
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... MT9171/72 transfer the D-channel in channel 0 and the C- channel in channel 16 or vice versa. One other feature exists; ODE, where both the DV and CD ports are tristated in order that no devices are damaged due to excessive loading while all DNICs are in a random state on power daisy chain arrangement ...
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... In MOD mode, the CD port is no longer an ST-BUS but is a serial bit stream operating at the bit rate bit 2 bit 3 bit 4 DRR BRS DINB Default Mode Selection (Refer to Table 4a) Description Table 4. Control Register MT9171/72 c hannel is In order to use the bit 5 bit 6 bit 7 PSEN ATTACK TxHK 9-143 ...
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... MT9171/72 C-Channel Internal Control (Bit 0-7) Register XXX01111 00000000 XXX11111 00010000 Notes: Default Mode 1 can also be selected by tying CDSTi/CDi pin low when DNIC is operating in dual mode. Default Mode 2 can also be selected by tying CDSTi/CDi pin high when DNIC is operating in dual mode. bit 0 bit 1 ...
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... Future Functionality. These bits return Logic 1 when read This bit provides a hardware identifier for the DNIC revision. The MT9171/72 will return a logic “0” for this bit. (Logic “1” returned for MT8972A.) transitions occur midway through the bit cell with a negative going transition indicating a logic " ...
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... MT9171/72 Bits Bit 7 Bit Data NRZ Data Differential Encoded ...
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... DC voltage at L C2’ = 1 MUR405 L OUT R2 = 390 10.24 MHz XTAL C3=33pF=C4 Note: Low leakage diodes (1 & 2) are required so that the DC voltage at L MT9171/72 For 80 kbit/s: C2’ Line Feed Voltage 68 Volts (Typ) 1.0 F 2.5 Joules 0.02 Watt V IN Bias For 80 kbit/s: C2’ = 3.3 nF 2:1 1.0 F ...
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... MT9171/72 Absolute Maximum Ratings Parameter 1 Supply Voltage 2 Voltage on any pin (other than supply) 3 Current on any pin (other than supply) 4 Storage Temperature 5 Package Power Dissipation (Derate 16mW/°C above 75°C) ** Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ...
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... F0S t 50 F0H t 244 F0W J -15 + Fig. 17) is not critical and may vary from (see Figure 17). C Channel 0 Channel 0 Bit 7 Bit 6 MT9171/72 ) unless otherwise stated. SS Units Test Conditions =160 kHz µ Baud =160 kHz Baud MHz ppm ...
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... MT9171/72 2.0V C4 0.8V 2.0V F0 0.8V Figure Clock & Frame Pulse Alignment for ST-BUS Streams in DN Mode 2.0V C4 0.8V 3.0V OSC1 2.0V Figure 17 - Frequency Locking for the C4 and OSC1 Clocks in MAS/DN Mode AC Electrical Characteristics Characteristics 1 TCK/RCK Clock Period 2 TCK/RCK Clock Width 3 TCK/RCK Clock Transition Time 4 CLD to TCK Setup Time ...
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... CDo Data Delay Time † Timing is over recommended temperature & power supply voltage ranges. * Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing. Performance Characteristics of the MT9171 DSIC Characteristics 1 Allowable Attenuation for Bit Error ...
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... MT9171/72 Figure 20 - Data Timing for Master Modem Mode 9-152 Advance Information ...
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... Advance Information 2.4V TCK 0.4V 2.0V Di CDI 0.8V 2.4V CDo 0.4V RCK 2.4V Do 0.4V Figure 21 - Data Timing for Slave Modem Mode ¼ MT9171/ 9-153 ...
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... MT9171/72 Notes: 9-154 Advance Information ...