MT9M019 Aptina Imaging Corporation, MT9M019 Datasheet - Page 10

• Manufacturer Part Number: MT9M019
• Description: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
• Manufacturer: Aptina Imaging Corporation

Message Byte
Acknowledge Bit
No-Acknowledge Bit
Typical Sequence
PDF: 7723845879/Source:2828556980
MT9M019 DS - Rev. F 5/10 EN
in accordance with the SMIA specification. Alternate slave addresses of 0x30 (write
address) and 0x31 (read address) can be selected by asserting the S
through GPI inputs or register programmable.
An alternate slave address can be programmed through R0x30FC–D.
Message bytes are used for sending register addresses and register write data to the slave
device and for retrieving register read data. The protocol used is outside the scope of the
I
Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the
SCLK clock period following the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases S
edge bit by driving S
LOW and must be stable while SCLK is HIGH.
The no-acknowledge bit is generated when the receiver does not drive S
during the SCLK clock period following a data transfer. A no-acknowledge bit is used to
terminate a read sequence.
A typical read or write sequence begins by the master generating a start condition on the
bus. After the start condition, the master sends the 8-bit slave address/data direction
byte. The last bit indicates whether the request is for a read or a write, where a “0” indi-
cates a write and a “1” indicates a read. If the address matches the address of the slave
device, the slave device acknowledges receipt of the address by generating an acknowl-
edge bit on the bus.
If the request was a write, the master then transfers the 16-bit register address to which
the write should take place. This transfer takes place as two 8-bit sequences and the
slave sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master then transfers the data as an 8-bit sequence; the slave sends an
acknowledge bit at the end of the sequence. The master stops writing by generating a
(re)start or stop condition.
If the request was a read, the master sends the 8-bit write slave address/data direction
byte and 16-bit register address, the same way as with a write request. The master then
generates a (re)start condition and the 8-bit read slave address/data direction byte, and
clocks out the register data, 8 bits at a time. The master generates an acknowledge bit
after each 8-bit transfer. The slave’s internal register address is auto-incremented after
every 8 bits are transferred. The data transfer is stopped when the master sends a no-
acknowledge bit.
2
C specification and is defined as part of the SMIA CCI.
DATA
LOW. As for data transfers, S
10
MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
DATA
. The receiver indicates an acknowl-
Two-Wire Serial Register Interface
Aptina reserves the right to change products or specifications without notice.
DATA
can change when SCLK is
©2006 Aptina Imaging Corporation. All rights reserved.
ADDR
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DATA
input signal
LOW