MT9M019 Aptina Imaging Corporation, MT9M019 Datasheet - Page 9

• Manufacturer Part Number: MT9M019
• Description: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
• Manufacturer: Aptina Imaging Corporation

Two-Wire Serial Register Interface
Protocol
Start Condition
Stop Condition
Data Transfer
Slave Address/Data Direction Byte
PDF: 7723845879/Source:2828556980
MT9M019 DS - Rev. F 5/10 EN
The two-wire serial interface bus enables read/write access to control and status regis-
ters within the MT9M019. This interface is designed to be compatible with the SMIA 1.0
Part2: CCP2 Specification camera control interface (CCI) which uses the electrical char-
acteristics and transfer protocols of the I
The interface protocol uses a master/slave model in which a master controls one or
more slave devices. The sensor acts as a slave device. The master generates a clock
(SCLK) that is an input to the sensor and used to synchronize transfers. Data is trans-
ferred between the master and the slave on a bidirectional signal (S
up to V
LOW—the interface protocol determines which device is allowed to drive S
given time.
The protocols described in the I
LOW. However, the MT9M019 uses SCLK as an input only and therefore never drives it
LOW.
Data transfers on the two-wire serial interface bus are performed by a sequence of low-
level protocol elements, as follows:
• a (repeated) start condition
• a slave address/data direction byte
• an (a no) acknowledge bit
• a message byte
• a stop condition
The bus is idle when both SCLK and S
a start condition, and the bus is released with a stop condition. Only the master can
generate the start and stop conditions.
A start condition is defined as a HIGH-to-LOW transition on S
HIGH. At the end of a transfer, the master can generate a start condition without previ-
ously generating a stop condition; this is known as a “repeated start” or “restart” condi-
tion.
A stop condition is defined as a LOW-to-HIGH transition on S
Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of
data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte and for message bytes.
One data bit is transferred during each SCLK clock period. S
is LOW and must be stable while SCLK is HIGH.
Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data
transfer direction. A “0” in bit [0] indicates a write, and a “1” indicates a read. The default
slave addresses used by the MT9M019 are 0x20 (write address) and 0x21 (read address)
DD
off-chip by a 1.5KΩ resistor. Either the slave or master device can drive S
9
MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
2
C specification enable the slave device to drive SCLK
DATA
2
C specification.
are HIGH. Control of the bus is initiated with
Two-Wire Serial Register Interface
Aptina reserves the right to change products or specifications without notice.
DATA
DATA
DATA
©2006 Aptina Imaging Corporation. All rights reserved.
can change when SCLK
DATA
while SCLK is HIGH.
while SCLK an is
). S
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DATA
DATA
is pulled
at any
DATA