SST25VF512A SST, SST25VF512A Datasheet - Page 4

• Manufacturer Part Number: SST25VF512A
• Description: 512 Kbit SPI Serial Flash
• Manufacturer: SST

Data Sheet
PRODUCT IDENTIFICATION
TABLE 2: P
MEMORY ORGANIZATION
The SST25VF512A SuperFlash memory array is orga-
nized in 4 KByte sectors with 32 KByte overlay blocks.
©2006 Silicon Storage Technology, Inc.
Manufacturer’s ID
Device ID
FIGURE 2: SPI P
SST25VF512A
SCK
CE#
SO
SI
RODUCT
MODE 3
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
ROTOCOL
I
DENTIFICATION
HIGH IMPEDANCE
Address
00000H
00001H
Data
BFH
48H
T2.0 1264
4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DEVICE OPERATION
The SST25VF512A is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consist of four control lines; Chip Enable (CE#) is used to
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
The SST25VF512A supports both Mode 0 (0,0) and Mode
3 (1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 2, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.
DON'T CARE
512 Kbit SPI Serial Flash
MODE 3
MODE 0
SST25VF512A
1264 F02.0
S71264-02-000
1/06