SST25VF512A SST, SST25VF512A Datasheet - Page 9

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SST25VF512A

Manufacturer Part Number
SST25VF512A
Description
512 Kbit SPI Serial Flash
Manufacturer
SST
Datasheet

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512 Kbit SPI Serial Flash
SST25VF512A
Read (20 MHz)
The Read instruction outputs the data starting from the
specified address location. The data output stream is con-
tinuous through all addresses until terminated by a low to
high transition on CE#. The internal address pointer will
automatically increment until the highest memory address
is reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space, i.e. for
©2006 Silicon Storage Technology, Inc.
FIGURE 4: R
SCK
CE#
SO
SI
MODE 3
MODE 0
EAD
MSB
0 1 2 3 4 5 6 7 8
S
EQUENCE
03
HIGH IMPEDANCE
MSB
ADD.
15 16
ADD.
23 24
ADD.
9
4 Mbit density, once the data from address location
7FFFFH had been read, the next output will be from
address location 00000H.
The Read instruction is initiated by executing an 8-bit com-
mand, 03H, followed by address bits [A
remain active low for the duration of the Read cycle. See
Figure 4 for the Read sequence.
MSB
31 32
D
OUT
N
39 40
D
N+1
OUT
47 48
D
N+2
OUT
55 56
D
N+3
OUT
63 64
D
N+4
1264 F04.0
OUT
S71264-02-000
23
-A
70
0
]. CE# must
Data Sheet
1/06

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