ISL51002 Intersil Corporation, ISL51002 Datasheet - Page 6

• Manufacturer Part Number: ISL51002
• Description: 10-Bit Video Analog Front End
• Manufacturer: Intersil Corporation

Timing Diagrams
Data Output Setup and Hold Timing
RGB Output Data Timing and Latency
YUV Output Data Timing and Latency
PIXEL DATA
DATACLK
R/G/B[9:0]
VIDEO IN
DATACLK
ANALOG
HSYNC
DATACLK
DATACLK
VIDEO IN
ANALOG
HSYNC
G[9:0]
R[9:0]
B[9:0]
HS
HS
OUT
OUT
IN
IN
P
P
0
0
6
P
P
1
1
8 DATACLK PIPELINE LATENCY
8 DATACLK PIPELINE LATENCY
P
P
2
2
THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED TO.
THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST OF THE
AFE’S OUTPUT SIGNALS
THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED
TO. THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST
OF THE AFE’S OUTPUT SIGNALS
t
SETUP
P
P
3
3
ISL51002
P
W IDTH AND POLARITY
P
4
4
PROGRAMMABLE
t
HOLD
WIDTH AND POLARITY
PROGRAMMABLE
P
P
5
5
P
P
6
6
P
P
7
7
P
P
8
8
G
B
0
0
D
(U
(Y
0
P
O
O
P
) G
) R
9
9
1
0
D
(V
(Y
1
P
P
1
0
10
)
) G
10
B
2
2
D
(U
(Y
P
2
P
2
2
December 22, 2006
11
)
)
11
G
R
3
2
D
(Y
(V
P
3
P
3
2
12
)
)
12