ISL51002 Intersil Corporation, ISL51002 Datasheet - Page 8

• Manufacturer Part Number: ISL51002
• Description: 10-Bit Video Analog Front End
• Manufacturer: Intersil Corporation

Pin Description
HSYNC
VSYNC
SOG
VREF
CLOCKINV
G
R
B
HSYNC
VSYNC
VREF
VREF
EXTCLK
XCLK
DATACLK
DATACLK
SYMBOL
COAST
CLAMP
XTAL
IN
IN
IN
FBC
SADDR
RESET
XTAL
HS
FBC
G[9:0]
IN
R[9:0]
B[9:0]
0, 1, 2, 3
0, 1, 2, 3
0, 1, 2, 3
SDA
SCL
IN
IN
GREEN
0, 1, 2, 3
OUT
OUT
BLUE
RED
0, 1, 2, 3
0, 1, 2, 3
OUT
OUT
IN
IN
OUT
OUT
IN
IN
IN
IN
,
,
Analog inputs. Red channels. AC couple through 0.1µF.
Analog inputs. Green channels. AC couple through 0.1µF.
Analog inputs. Blue channels. AC couple through 0.1µF.
Analog inputs. Reference voltage for ADCs. Tie to 1.8V reference voltage (V
0.1µF capacitor to GND
Analog inputs. Sync on Green. Connect to corresponding Green channel video source through a 0.01µF capacitor in
series with a 500Ω resistor.
Digital high impedance 3.3V inputs with 240mV hysteresis. Connect to corresponding channel's HSYNC source. For 5V
signals divide input with a 1k/1.9k divider. Place the divider as close as possible to the device pin. Place a 50pFcapacitor
in parallel with the 1k resistor to reduce the filtering effect of the divider.
Digital high impedance 3.3V inputs with 240mV hysteresis. Connect to corresponding channel's VSYNC source. For 5V
signals divide input with a 1k/1.9k divider. Place the divider as close as possible to the device pin. Place a 50pF capacitor
in parallel with the 1k resistor to reduce the filtering effect of the divider.
Digital 3.3V input. When this input is high and external COAST is selected, the PLL will coast, ignoring all transistions on
the active channel’s HSYNC/SOG.
Digital 3.3V input.When this input is high and external CLAMP is selected, connects the selected channels inputs to the
clamp DAC.
Digital 3.3V input. When high, changes the pixel sampling phase by +180°. Toggle at frame rate during VSYNC to allow
2x undersampling to sample odd and even pixels on sequential frames. Tie to D
Digital 3.3V input.Connect to the Fast Blank signal of a SCART connector.
3.3V digital output. A delayed version of the FBC
Digital 3.3V input, active low, 70kΩ pullup to V
pin is not necessary for normal use and may be tied directly to the V
Analog input. Connect to external 12MHz to 27MHz crystal and load capacitor (see crystal spec for recommended
loading). Typical oscillation amplitude is 1.0V
Analog output. Connect to external 12MHz to 27MHz crystal and load capacitor (see crystal spec for recommended
loading). Typical oscillation amplitude is 1.0V
3.3V digital output. Buffered crystal clock output at f
components.
Digital 3.3V input. Address = 0x98 (1001100x) when tied low.
Address = 0 x 9A (1001101x) when tied high.
Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
Digital 3.3V input. External clock input for AFE.
3.3V digital output. 10-bit Red channel pixel data.
3.3V digital output. 10-bit Green channel pixel data.
3.3V digital output. 10-bit Blue channel pixel data.
3.3V digital output. Data (pixel) clock output.
3.3V digital output. Inverse of DATACLK.
3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data. This output is
always purely horizontal sync (without any composite sync signals)
3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used for measuring HSYNC period. This
output will pass composite sync signals and Macrovision signals if present on HSYNC
3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the duration of the
disruption of the normal HSYNC pattern. This is typically used for measuring VSYNC period.
8
A
.
ISL51002
P-P
P-P
D
. Take low for at least 1µs and then high again to reset the ISL51002. This
IN
centered around 0.5V.
centered around 0.5V.
signal, aligned with the digital pixel data.
XTAL
DESCRIPTION
or f
XTAL
/2. May be used as system clock for other system
D
supply.
A1.8
is acceptable if low noise). Decouple with
GND
if unused.
IN
or SOG
IN
.
December 22, 2006