ISL6522A Intersil Corporation, ISL6522A Datasheet - Page 7

• Manufacturer Part Number: ISL6522A
• Description: Buck and Synchronous Rectifier Pulse-Width Modulator (PWM) Controller
• Manufacturer: Intersil Corporation

Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous rectified buck converter. The output voltage
(V
amplifier (error amp) output (V
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V
PHASE node. The PWM wave is smoothed by the output filter
(L
The modulator transfer function is the small-signal transfer
function of V
gain and the output filter (L
break frequency at F
the modulator is simply the input voltage (V
peak-to-peak oscillator voltage ∆V
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6522A) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
F
F
F
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
LC
Z1
Z2
O
OUT
C
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
SS
SS
(~75% F
and C
=
=
=
FB
) is regulated to the reference voltage level. The error
-------------------------------------- -
2π
----------------------------------
2π R
----------------------------------------------------- -
2π
. The goal of the compensation network is to provide
•
ISL6522A
O
•
•
GND
ST
).
(
0dB
L
OUT
R1
1
1
LC
2 C1
O
LAYOUT GUIDELINES
Zero Below Filter’s Double Pole
•
)
•
) and adequate phase margin. Phase margin
+
1
/V
C
R3
O
E/A
) C3
LC
•
C
PHASE
VCC
BOOT
. This function is dominated by a DC
BOOT
and a zero at F
+12V
O
F
and C
C
ESR
7
E/A
F
F
VCC
D1
P1
P2
=
) is compared with the
OSC
=
O
=
-------------------------------------------- -
2π
), with a double pole
----------------------------------
2π R3 C3
------------------------------------------------------ -
2π R2
.
•
ESR
(
•
Q1
•
+V
Q2
ESR C
1
IN
IN
1
. The DC gain of
L
•
) divided by the
•
O
•
IN
1


C
--------------------- -
C1
C1 C2
O
at the
O
)
+
•
0dB
C2
V


OUT
and
IN
ISL6522A
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain is constructed on the log-log
graph of Figure 8 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
FB
∆V
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
and Z
OSC
OSC
IN
ND
ST
ND
COMPARATOR
to provide a stable, high bandwidth (BW) overall
COMPENSATION DESIGN
ERROR
AMP
V
Pole at the ESR Zero
ISL6522A
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
E/A
DETAILED COMPENSATION COMPONENTS
PWM
Z
+
-
COMP
FB
+
-
C1
P2
REFERENCE
C2
with the capabilities of the error
+
-
R2
DRIVER
DRIVER
REF
Z
IN
Z
FB
FB
V
IN
PHASE
C3
(PARASITIC)
Z
L
IN
R1
O
R3
ESR
C
V
O
OUT
V
OUT