ISL6522A Intersil Corporation, ISL6522A Datasheet - Page 9

• Manufacturer Part Number: ISL6522A
• Description: Buck and Synchronous Rectifier Pulse-Width Modulator (PWM) Controller
• Manufacturer: Intersil Corporation

should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
For a through-hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX
or equivalent) may be needed. For surface mount designs, solid
tantalum capacitors can be used, but caution must be exercised
with regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. The TPS series available from AVX, and the 593D
series from Sprague are both surge current tested.
MOSFET Selection/Considerations
The ISL6522A requires two N-Channel power MOSFETs.
These should be selected based upon r
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor. The switching losses seen when
sourcing current will be different from the switching losses seen
when sinking current. When sourcing current, the upper
MOSFET realizes most of the switching losses. The lower
switch realizes most of the switching losses when the converter
is sinking current (see the equations below).
These equations assume linear voltage-current transitions and
do not adequately model power loss due the reverse-recovery
of the upper and lower MOSFET’s body diode. The gate-charge
losses are dissipated by the ISL6522A and do not heat the
MOSFETs. However, large gate-charge increases the switching
interval, t
losses. Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package thermal-
resistance specifications. A separate heatsink may be
necessary depending upon MOSFET power, package type,
ambient temperature and air flow.
Losses while Sinking Current
Losses while Sourcing Current
P
P
P
P
UPPER
LOWER
LOWER
UPPER
Where: D is the duty cycle = V
SW
= Io
= Io
=
=
t
F
which increases the upper MOSFET switching
SW
Io
S
Io
2
2
2
is the switching frequency.
x r
2
x r
is the switching interval, and
×
×
DS(ON)
DS(ON)
r
r
DS ON
DS ON
(
(
x D
x (1 - D)
)
)
×
×
D
(
1 D
+
9
–
1
-- - Io
2
OUT
⋅
)
+
/ V
×
1
-- - Io
2
V
⋅
IN
IN
DS(ON)
,
×
×
V
t
SW
IN
, gate supply
×
×
t
F
SW
S
×
F
S
ISL6522A
Standard-gate MOSFETs are normally recommended for
use with the ISL6522A. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFETs absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from V
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V
less the boot diode drop (V
turns on. A logic-level MOSFET can only be used for Q1 if
the MOSFETs absolute gate-to-source voltage rating
exceeds the maximum voltage applied to V
logic-level MOSFET can be used if its absolute gate-to-
source voltage rating exceeds the maximum voltage applied
to PVCC.
FIGURE 10. UPPER GATE DRIVE - DIRECT V
Figure 10 shows the upper gate drive supplied by a direct
connection to V
converter systems where the main input voltage is +5V
less. The peak upper gate-to-source voltage is approximately
ISL6522A
+
ISL6522A
+
-
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
-
+12V
+12V
VCC
VCC
CC
+
GND
D
GND
. This option should only be used in
V
BOOT
D
BOOT
UGATE
PHASE
LGATE
PGND
PVCC
BOOT
UGATE
PHASE
LGATE
PGND
PVCC
-
+5V
CC
+5V
OR +12V
OR +12V
D
C
. The boot capacitor, C
) when the lower MOSFET, Q2
BOOT
Q1
Q2
Q1
+5V OR +12V
Q2
+5V OR LESS
D2
CC
CC
D2
NOTE:
V
V
NOTE:
NOTE:
V
NOTE:
V
G-S
G-S
DRIVE OPTION
. For Q2, a
G-S
G-S
≈ V
≈ V
≈ PVCC
≈ PVCC
BOOT
CC
CC
DC
- V
- 5V
or
CC
D