ISL95711 Intersil Corporation, ISL95711 Datasheet
ISL95711
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ISL95711 Summary of contents
Page 1
... Data Sheet Terminal Voltage ±3V or ±5V, 128 Taps I Serial Interface The Intersil ISL95711 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The 2 wiper position is controlled interface. The potentiometer is implemented by a resistor array composed of 127 resistive elements and a wiper switching network ...
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... The wiper terminal which is equivalent to the movable terminal of a potentiometer fixed terminal for one end of the potentiometer resistor Positive logic supply voltage CC 10 SCL Clock input for the I 2 ISL95711 7-BIT SDA WIPER REGISTER SCL (VOLATILE) 7-BIT NONVOLATILE MEMORY DECODER STORE AND ...
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... RESISTOR MODE (Measurements between R RINL Integral non-linearity (Note 11) RDNL Differential non-linearity (Note 10) Roffset Offset (Note 9) TC Resistance Temperature Coefficient R (Notes 12, 13) 3 ISL95711 Recommended Operating Conditions Temperature Range (Industrial .-40°C to +85° 5. -3V to -5.5V +0. TEST CONDITIONS W option U option V- = -5.5V +5.5V, wiper current = CC ...
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... AA valid t Time the bus must be free before the BUF start of a new transmission t Clock LOW time LOW 4 ISL95711 TEST CONDITIONS 2 = 400kHz;SDA = Open; (for I SCL Read and Volatile Write States only 400kHz;SDA = Open; (for I SCL Read and Volatile Write States only) ...
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... SDA vs SCL Timing SCL t SU:STA t HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) 5 ISL95711 TEST CONDITIONS Measured at the 70 crossing. CC SCL rising edge to SDA falling edge. Both crossing 70 From SDA falling edge crossing 30 SCL falling edge crossing 70 From SDA exiting the 30 ...
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... These are I C specific parameters and are not directly tested, however they are used during device testing to validate device specification. 6 ISL95711 Clk 1 5V supply voltage. and V(RW) are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the ...
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... R closest to R and R L between R While the ISL95711 is being powered up, the WR is reset to 40h (64 decimal), which locates the R and V-. For proper CC stabilization. As the V- CC pin goes to the default W also exceeds 2.5V (after V- < ...
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... Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are 2 C interface reserved for indicating START and STOP conditions (See Figure 1). On power-up of the ISL95711 the SDA pin is in the input mode. 2 All I C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH ...
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... Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL95711 responds with an ACK. At this time, if the Data Byte written only to volatile registers, then the device enters its standby state. If the Data Byte written also to non-volatile memory, the ISL95711 begins its internal write cycle to non-volatile memory ...
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... SIGNALS FROM THE SLAVE Communicating with the ISL95711 There are 3 register addresses in the ISL95711, of which two can be used. Address 00h and address 02h are used to control the device. Address 01h is reserved and should not be used. Address 00h contains the non-volatile Initial Value Register (IVR), and the volatile Wiper Register (WR) ...
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... Reading from the WR: Write to the ACR first (to index the WR Then, Set the WR address Read from the NOTE acknowledge data bit read 11 ISL95711 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 ISL95711 10 Lead MSOP, Package Code 0.0106 [0.27] 4 ...