ISL95711 Intersil Corporation, ISL95711 Datasheet - Page 9

• Manufacturer Part Number: ISL95711
• Description: 128 Taps I2C Serial Interface
• Manufacturer: Intersil Corporation

Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL95711 responds with an ACK. At this time, if the Data
Byte is to be written only to volatile registers, then the device
enters its standby state. If the Data Byte is to be written also
to non-volatile memory, the ISL95711 begins its internal write
cycle to non-volatile memory. During the internal non-volatile
write cycle, the device ignores transitions at the SDA and
SCL pins, and the SDA output is at a high impedance state.
When the internal non-volatile write cycle is completed, the
ISL95711 enters its standby state (See Figure 3).
The byte at address 02h determines if the Data Byte is to be
written to volatile or both volatile and non-volatile. (See
“Memory Description” on page 8.)
Data Protection
A STOP condition acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile
and non-volatile registers. During a Write sequence, the
Data Byte is loaded into an internal shift register as it is
SDA OUTPUT FROM
SDA OUTPUT FROM
TRANSMITTER
SCL FROM
RECEIVER
SDA
SCL
MASTER
9
START
FIGURE 1. VALID DATA CHANGES, START, AND STOP CONDITIONS
START
FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER
HIGH IMPEDANCE
1
STABLE
DATA
ISL95711
CHANGE
DATA
received. If the Address Byte is 0 or 2, the Data Byte is
transferred to the Wiper Register (WR) or to the Access
Control Register respectively, at the falling edge of the SCL
pulse that loads the last bit (LSB) of the Data Byte. If the
Address Byte is 0, and the Access Control Register is all
zeros (default), then the STOP condition initiates the internal
write cycle to non-volatile memory.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (See Figure 4). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL95711 responds with an ACK; then
the ISL95711 transmits the Data Byte. The master then
terminates the read operation (issuing a STOP condition)
following the last bit of the Data Byte (See Figure 4).
The byte at address 02h determines if the Data Bytes being
read are from volatile or non-volatile memory. (See “Memory
Description”.)
STABLE
DATA
8
HIGH IMPEDANCE
STOP
ACK
9
August 15, 2005
FN8241.2