SMB118 SUMMIT Microelectronics, Inc:, SMB118 Datasheet - Page 31

• Manufacturer Part Number: SMB118
• Description: Six-channel Programmable Dc-dc Power Managers With Battery Charger
• Manufacturer: SUMMIT Microelectronics, Inc:

SERIAL INTERFACE
Access to the configuration registers, general-purpose
memory and command and status registers is carried
out over an industry standard 2-wire serial interface
(I
clock input. Data is clocked in on the rising edge of
SCL and clocked out on the falling edge of SCL. All
data transfers begin with the MSB.
transfers, SDA must remain stable while SCL is high.
Data is transferred in 8-bit packets with an intervening
clock period in which an Acknowledge is provided by
the device receiving data. The SCL high period (t
is used for generating Start and Stop conditions that
precede and end most transactions on the serial bus.
A high-to-low transition of SDA while SCL is high is
considered a Start condition while a low-to-high
transition of SDA while SCL is high is considered a
Stop condition.
The interface protocol allows operation of multiple
devices and types of devices on a single bus through
unique device addressing.
comprised of a 7-bit device type identifier (slave
address). The remaining bit indicates either a read or
a write operation. Refer to Table 1 for a description of
the address bytes used by the SMB118 and SMB218.
The device type identifier for the memory array, the
configuration registers and the command and status
registers are accessible with the same slave address.
The slave address can be can be programmed to any
seven bit number 0000000
WRITE
Writing to the memory or a configuration register is
illustrated in Figures 15, 16, 18, and 19.
condition followed by the slave address byte is
provided by the host; the SMB118 responds with an
Acknowledge; the host then responds by sending the
memory address pointer or configuration register
address pointer; the SMB118 and SMB218 respond
with an acknowledge; the host then clocks in one byte
of data. For memory and configuration register writes,
up to 15 additional bytes of data can be clocked in by
the host to write to consecutive addresses within the
same page.
Summit Microelectronics, Inc
2
I
C). SDA is a bi-directional data line and SCL is a
2
C PROGRAMMING INFORMATION
BIN
through 1111111
The address byte is
During data
BIN
A Start
.
HIGH
2107 2.4 5/5/2008
)
an Acknowledge, a Stop condition must be issued to
initiate the nonvolatile write operation.
READ
The address pointer for the non-volatile configuration
registers and memory registers as well as the volatile
command and status registers must be set before data
can be read from the SMB118 and SMB218. This is
accomplished by issuing a dummy write command,
which is a write command that is not followed by a
Stop condition.
address from which data is read. After the dummy
write command is issued, a Start command followed
by the address byte is sent from the host. The host
then waits for an Acknowledge and then begins
clocking data out of the slave device. The first byte
read is data from the address pointer set during the
dummy write command.
clocked out of consecutive addresses with the host
providing an Acknowledge after each byte. After the
data is read from the desired registers, the read
operation is terminated by the host holding SDA high
during the Acknowledge clock cycle and then issuing a
Stop condition. Refer to Figures 17 and 20 for an
illustration of the read sequence.
CONFIGURATION REGISTERS
The configuration registers are grouped with the
general-purpose memory. Writing and reading the
configuration registers is shown in Figures 15, 16 and
17.
GENERAL-PURPOSE MEMORY
The 96-byte general-purpose memory block is
segmented into two continuous independently lockable
blocks. The first 48-byte memory block begins at
register address pointer A0
block begins at the register address pointer C0
Table 1. Each memory block can be locked
individually by writing to a dedicated register in the
configuration memory space. Memory writes and
reads are shown in Figures 18, 19 and 20.
After the last byte is clocked in and the host receives
A dummy write command sets the
HEX
Preliminary Specification
Additional bytes can be
and the second memory
SMB118/218
HEX
; see
31