74LVC169PW,112 NXP Semiconductors, 74LVC169PW,112 Datasheet - Page 14

• Manufacturer Part Number: 74LVC169PW,112
• Description: IC SYNC 4BIT BIN COUNTER 16TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: Binaryr

Specifications of 74LVC169PW,112

• Package / Case: 16-TSSOP
• Logic Type: Binary Counter
• Direction: Up, Down
• Number Of Elements: 1
• Number Of Bits Per Element: 4
• Timing: Synchronous
• Count Rate: 150MHz
• Trigger Type: Positive Edge
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Technology: CMOS
• Number Of Elements: 1
• Number Of Bits: 4
• Logic Family: LVC
• Logical Function: Counter
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Output Type: Standard
• Package Type: TSSOP
• Propagation Delay Time: 11ns
• Operating Temp Range: -40C to 125C
• Operating Supply Voltage (min): 1.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Reset: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 74LVC169PW; 74LVC169PW; 935210590112

NXP Semiconductors
Table 9.
[1]
74LVC169_5
Product data sheet
Supply voltage
1.2 V
2.7 V
3.0 V to 3.6 V
Fig 13. Test circuit for measuring switching times
The circuit preforms better when R
Test data is given in
Definitions for test circuit:
C
R
R
L
L
T
Test data
= Load capacitance including jig and probe capacitance.
= Load resistance
= Termination resistance should be equal to output impedance Z
Input
V
V
2.7 V
2.7 V
I
CC
Table
9.
negative
L
positive
= 1000 k .
pulse
pulse
0 V
0 V
V
V
I
I
t
r
, t
G
2.0 ns
2.5 ns
2.5 ns
90 %
10 %
f
V
I
t
t
Rev. 05 — 8 June 2009
f
r
V
V
M
M
10 %
90 %
R T
Presettable synchronous 4-bit up/down binary counter
V
DUT
CC
Load
C
30 pF
50 pF
50 pF
L
t
t
W
W
V
O
o
of the pulse generator.
C L
V
V
M
M
001aae331
t
t
V
r
f
EXT
R L
R L
R
500
500
500
L
[1]
74LVC169
© NXP B.V. 2009. All rights reserved.
S1 position
t
open
open
open
PLH
: t
PHL
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