ST7528 Sitronix, ST7528 Datasheet - Page 26

• Manufacturer Part Number: ST7528
• Description: 16 Gray Scale Dot Matrix LCD Controller
• Manufacturer: Sitronix

ST7528
IIC Interface protocol
The ST7528 supports command, data write addressed slaves on the bus.
Before any data is transmitted on the IIC Interface, the device, which should respond, is addressed first. Four 7-bit slave
addresses (0111100, 0111101, 0111110 and 0111111) are reserved for the ST7528. The least significant bit of the slave
address is set by connecting the input SA0 and SA1 to either logic 0 (VSS) or logic 1 (VDD).
The IIC Interface protocol is illustrated in Figure 6.
Note: ST7528 IIC interface can not use with other slaver IIC device
The sequence is initiated with a START condition (S) from the IIC Interface master, which is followed by the slave address.
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the IIC Interface transfer. After
acknowledgement, one or more command words follow which define the status of the addressed slaves.
A command word consists of a control byte, which defines Co and A0, plus a data byte.
The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a
cleared Co bit, only data bytes will follow. The state of the A0 bit defines whether the data byte is interpreted as a command
or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte,
depending on the A0 bit setting; either a series of display data bytes or command data bytes may follow. If the A0 bit is set
to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer
is automatically updated and the data is directed to the intended ST7528 device. If the A0 bit of the last control byte is set to
logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received
commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the IIC
INTERFACE-bus master issues a STOP condition (P).If the R/W bit is set to logic 1 the chip will output data immediately
after the slave address if the A0 bit, which was sent during the last write access, is set to logic 0. If no acknowledge is
generated by the master after a byte, the driver stops transferring data to the master.
Ver2.3
Co
S 0 1 1 1 1
Write mode
0
1
slave address
Last control byte to be sent. Only a stream of data bytes is allowed to follow.
This stream may only be terminated by s STOP or RE-START condition.
Another control byte will follow the data byte unless a STOP or RE-START condition is received.
S
A
1
acknowledgement
A
S
0
from ST7528
R/W
0 A
Co
1
0 1 1 1 1
A
0
slave address
control byte
acknowledgement
Figure 6 2-line Interface protocol
S
A
1
from ST7528
command word
2n>=0bytes
A
S
0
R
W
/
A
data byte
26/97
acknowledgement
from ST7528
www.DataSheet.co.kr
A
Co
0
A
0
Co
control byte
A
0
1 byte
0 0 0 0 0 0
control byte
acknowledgement
from ST7528
A
MSB.......................LSB
A
n>=0bytes
data byte
acknowledgement
from ST7528
A P
2007/1/3
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