ST7528 Sitronix, ST7528 Datasheet - Page 28

• Manufacturer Part Number: ST7528
• Description: 16 Gray Scale Dot Matrix LCD Controller
• Manufacturer: Sitronix

ST7528
DISPLAY DATA RAM (DDRAM)
When Mode 0 is selected
The Display Data RAM stores pixel data for the LCD. It is 129-row (17 pages by 8 bits) by 132-column addressable array.
Each pixel can be selected when the page and column addresses are specified. The 129 rows are divided into 16 pages of
8 lines and the 17th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly
through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines. The
microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently,
data can be written into RAM at the same time as data is being displayed without causing the LCD flicker.
When Mode 1 is selected
The Display Data RAM stores pixel data for the LCD. It is 101-row (13 pages by 8 bits) by 160-column addressable array.
Each pixel can be selected when the page and column addresses are specified. The 101 rows are divided into 12 pages of
8 lines and the 13th page with 4 lines; the Page Address 16 (17th page) is for Icon page with a single line (DB0 only). Data
is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the
microprocessor correspond to the LCD common lines. The microprocessor can read from and write to RAM through the I/O
buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being
displayed without causing the LCD flicker.
Page Address Circuit
In mode 0
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It incorporates 4-bit Page Address register changed by only the “Set Page” instruction. Page Address 16 is a special RAM
area for the icons and display data DB0 is only valid. The page address is set from 0 to 15, and Page 16 is for Icon page.
In mode 1
It incorporates 4-bit Page Address register changed by only the “Set Page” instruction. Page Address 16 is a special RAM
area for the icons and display data DB0 is only valid. The page address is set from 0 to 12, and Page 16 is for Icon page.
Line Address Circuit
In mode 0
This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line
Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of
on-chip RAM. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter
circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL
signal and generates the line address for transferring the 128-bit RAM data to the display data latch circuit. When icon is
enabled by setting icon control register, display data of icons are not scrolled because the MPU can not access Line
Address of icons.
In mode 1
The 7-bit Line Address register is set from 0 ~ 99, If the register is set from 100 ~ 127, It will be no operation. The register
value will be kept in last value.
Ver2.3
28/97
2007/1/3
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