ST7577 Sitronix Technology, ST7577 Datasheet
ST7577
Related parts for ST7577
ST7577 Summary of contents
Page 1
... Sitronix 1. INTRODUCTION ST7577 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. ST7577 contains 132 segment and 39 common driver circuits. This chip is connected directly to a microprocessor, accepts 3-line, 4-line serial peripheral interface (SPI) or 8-bit parallel interface, display data can stores in an on-chip Display Data RAM (DDRAM) of 132 x 39 bits. ...
Page 2
... ST7577 3. ST7577 Pad Arrangement (COG) Chip Size: 6074μm(X) x 720μm(Y) Chip Thickness: 480μm Bump Height: 15μm PAD Pitch: PAD Pitch PAD 1~5 60 40~49 5~6 84.5 49~50 6~11 60 50~72 11~12 84.5 72~73 12~39 60 73~96 39~40 89 96~97 Rough layout l For easy LCM design, the Power-1, Power-2 & Power-3 are identical (any one of them can be used). ...
Page 3
... ST7577 4. Pad Center Coordinates PAD No. PAD Name X 1 VDD2 -2899.00 2 VDD2 -2839.00 3 VDD -2779.00 4 VDD -2719.00 5 VDD -2659.00 6 dummy -2574.50 7 dummy -2514.50 8 dummy -2454.50 9 dummy -2394.50 10 dummy -2334.50 11 dummy -2274.50 12 CSB_A -2190.00 13 A0_A -2130.00 14 RWR_A -2070.00 15 ERD_A -2010.00 16 D0_A -1950.00 17 D1_A -1890 ...
Page 4
... ST7577 PAD No. PAD Name X 91 VDD 2599.00 92 VDD 2659.00 93 VDD2 2719.00 94 VDD2 2779.00 95 VDD2 2839.00 96 VDD2 2899.00 97 VDD2 2982.00 98 VGO 2982.00 99 VGO 2982.00 100 VSS 2982.00 101 VSS 2982.00 102 COM[38] 2913.00 103 COM[37] 2879.00 104 COM[36] 2845.00 105 COM[35] 2811.00 ...
Page 5
... ST7577 PAD No. PAD Name X 181 SEG[60] 204.00 182 SEG[61] 170.00 183 SEG[62] 136.00 184 SEG[63] 102.00 185 SEG[64] 68.00 186 SEG[65] 34.00 187 SEG[66] 0.00 188 SEG[67] -34.00 189 SEG[68] -68.00 190 SEG[69] -102.00 191 SEG[70] -136.00 192 SEG[71] -170.00 193 SEG[72] -204.00 194 SEG[73] -238.00 ...
Page 6
... ST7577 PAD No. PAD Name X 271 COM[18] -2879.00 272 COM[19] -2913.00 273 VSS -2982.00 274 VSS -2982.00 275 VGO -2982.00 276 VGO -2982.00 277 VDD2 -2982.00 * Unit: μm * “dummy” pads are floating and not connected to any part of circuits. * Please refer to Page6 for detail output Map (especially for 1/12 & 1/39 duty). ...
Page 7
... ST7577 5. BLOCK DIAGRAM Voltage VM Follower VGI VG VGO Generator VGS XV0I XV0 XV0O Generator XV0S V0I V0 V0O Generator V0S Power PM System V DD2 Reset Circuit Ver 1.0a SEG0...SEG131 COM0...COM38 SEGMENT COMMON Drivers Drivers COMMON Display Data Latchs Controller Display Data RAM ...
Page 8
... ST7577 6. PIN DESCRIPTION Pin Name I/O LCD DRIVER OUTPUTS LCD segment driver outputs. This display data and the M signal control the output voltage of segment driver. SEG0…SEG131 O LCD column driver outputs. This internal scanning data and M signal control the output voltage of common driver. ...
Page 9
... ST7577 Read/Write execution control pin (PS[0:1]=[L:H]). RWR_A (for Port-A) I RWR_B (for Port-B) When in the serial interface, left it connected MODE pin will select one of two RWR pins. The unused one should be left floating. Read/Write execution control pin (PS[0:1]=[L:H]). ERD_A (for Port-A) I ERD_B (for Port-B) When in the serial interface, left it connected MODE pin will select one of two RWR pins ...
Page 10
... ST7577 LCD DRIVER CLOCK SUPPLY When the on-chip oscillator is used, this input must be connected to V oscillator and external clock are both inhibited by connecting the OSC pin OSC avoid this, the chip should always be put into Power Down Mode before stopping the clock. ...
Page 11
... TEST PIN T0~T8 left them open. T0~T9 Test T9 must connect to V ST7577 has 2 sets of interface port (Port-A & Port-B). These two ports can be selected by “MODE” pin. l Port-A and Port-B are identical (CSB, A0, /RW, /RD, D7~D0) except RESB pin. l The unused pins should be left floating. ...
Page 12
... Chip Select Input The CSB pin is used for chip selection. ST7577 can interface with an MPU when CSB is "L". When CSB is “H”, the control pins (A0, /RD and /WR) are disabled and are set to be high impedance. If using serial interface, the internal shift register and the counter are reset when CSB=” ...
Page 13
... PS2=“L”, PS1=“L”, PS0=“L”: 4-line SPI interface When ST7577 is set into 4-line SPI interface mode, setting CSB to be “L” will active this chip. If CSB is “H”, the internal 8-bit shift register and a 3-bit counter are reset. When CSB is “L”, the serial data (SDA) and the serial clock (SCLK) are set into input mode. The input signal on SDA will be latched into the shift register from the rising edge of the serial clock. The display data/instruction indication is controlled via the register select pin: A0. If A0=” ...
Page 14
... ST7577 Data Transfer ST7577 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Figure 4. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in Figure 5 ...
Page 15
... RAM at the same time as data is being displayed without causing the LCD flicker or data-conflict. DDRAM ORGANIZATION Data is written in bytes into the RAM matrix of ST7577 as shown in Figure 6~Figure 9. The Display Data RAM is a matrix of 132 by 39 bits. The address pointer keeps the X and Y address. The valid address ranges are: X=0~131, Y=0~4. ...
Page 16
... DDRAM are transferred to the Display Data Latch Circuit at the beginning of each frame. ADDRESSING ST7577 will automatically increases the address when sequential access. This feature allows MPU to access the display data in DDRAM continuously without setting the address before each access. ...
Page 17
... ST7577 LCD DRIVER DISPLAY DIRECTION Register bits XD (horizontal direction) and MY (vertical mirror) control the horizontal and vertical display direction. XD controls the X-address write direction in DDRAM while MY controls the common output direction. Therefore necessary to rewrite the display data to DDRAM after changing XD-bit setting. Refer to the following figure. ...
Page 18
... ST7577 DDRAM MAP vs. START LINE Ver 1.0a Figure 11 Display Data RAM Map (39 COM) 18/48 www.DataSheet4U.com 2008/02/14 ...
Page 19
... ST7577 LCD DRIVER CIRCUIT ST7577 built-in LCD driver circuit has 132-channel segment drivers and 39-channel common drivers. The LCD panel driving voltage depends on the combination of display data and M signal (frame indicator). The referential external component values are listed below (it is determined by the worse condition of 1.4” panel). ...
Page 20
... ST7577 PARTIAL DISPLAY (SOFTWARE) The Partial Display function is controlled by software instruction. This feature is only available under 1/39 duty mode (DTY=”L”). Although only 26 common outputs are used, the duty of Partial Display is not changed (1/39 Duty). Those unused commons output the non-selected waveform. ...
Page 21
... ST7577 Figure 17 Partial Display: Middle Mode ( DA1=1, DA0=0) Figure 18 Partial Display: Lower Mode ( DA1=1, DA0=1) Ver 1.0a 21/48 www.DataSheet4U.com -COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM31 -COM32 -COM33 -COM34 -COM35 -COM36 -COM37 -COM38 2008/02/14 ...
Page 22
... ST7577 8. RESET CIRCUIT Setting RESB to “L” can initialize internal function. While RESB is “L”, no instruction except read status can be accepted. The initialization by RESB is essential before using. When RESB becomes “L”, the following procedures will start. Fix COM/SEG outputs ...
Page 23
... ST7577 9. INSTRUCTION TABLE R/W INSTRUCTION A0 (/WR) H (Independent of H) NOP 0 0 Reset 0 0 Function Set 0 0 Read Status 0 1 Read Data 1 1 Write Data 1 0 R/W INSTRUCTION A0 (/WR) H=0 Reserved 0 0 End 0 0 read-modify-write Enable 0 0 read-modify-write Display Control 0 0 Frame Rate 0 0 Set Y address of ...
Page 24
... ST7577 10. INSTRUCTION DESCRIPTION Function Set A0 R/W(/WR Flag Set COM scan direction: MY MY=0: Normal direction (COM0->COM38, duty is determined by the MY=1: Reverse direction (COM38->COM0, duty is determined by the Set DDRAM write direction. XD XD=1: Write from X=0 to X=131 (Normal direction); XD=0: Write from X=131 to X=0 (Reverse direction). Set the power mode: PD=0: Chip is active ...
Page 25
... ST7577 Read Data Read the specified 8-bit data in DDRAM to the microprocessor. The location is specified by the X-address and Y-address. A0 R/W(/WR Write Data 8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page ...
Page 26
... ST7577 H=0 When Function Set instruction sets H=0, the selected instruction descriptions are as below. End Read-Modify-Write This command releases the Read-Modify-Write mode, and returns the column and row address to the address it was at when the mode was entered. A0 R/W(/WR Enable Read-Modify-Write This command is used paired with the ”End Read-Modify-Write” instruction. Once this command has been input, the display data read command does not change the column and row address, but only the display data write command increments (+1) the address depend on V register setting ...
Page 27
... ST7577 Frame Rate This command is used to select the frame rate. A0 R/W(/WR The optional Frame Rates are: (no matter 1/ 1/12 duty mode, the frame rate will be controlled in the specified range Set Y address of DDRAM Y[2:0] specifies the Y address of the Display Data RAM (DDRAM) ...
Page 28
... Booster Efficiency Level 2 (Default) 1 Booster Efficiency Level 1 ST7577 supports software selectable Booster Stage. Customers can change the BE[1:0] and PC[1:0] according to the LCD panel loading and their power consumption requirement. The higher stage generates higher driving ability while the power consumption is also higher. ...
Page 29
... ST7577 BIAS System ST7577 is built-in a BIAS-voltage generation system for driving the LCD. The bias can be specified by this instruction. A0 R/W(/WR The referential settings of Bias, Duty and V0 are listed below: (assume VDD2=2.8V) BS1 BS0 BIAS Recommend Duty Ver 1 ...
Page 30
... ST7577 Set V0 Set V0 voltage level into this register and the built-in voltage regulator will generate the V0. A0 R/W(/WR The V0 voltage can be calculated by this formula: The parameters in this formula are controlled by the hardware pin “PM” (Ta=25°C). H/W Setting PM=”L” PM=”H” ...
Page 31
... ST7577 11. Instruction Sequence This section introduces some reference instruction flows. Power ON flow with built-in power circuits: Figure 20 Initial flow with built-in Power Supply Circuits POWER SEQUENCE V2ON Period between VDD and VDD2 turned ON. => (min). No maximum value specified ON-RES RESB has priority over CSB ...
Page 32
... ST7577 Power Saving flow with built-in power circuits ENTERING THE POWER SAVE MODE The power save mode is achieved by setting PD bit to be “1”. No specified instruction flow required. EXITING THE POWER SAVE MODE INTERNAL SEQUENCE of EXIT POWER SAVE MODE After receiving the “PD” is “L”, the internal circuits (Power and COM/SEG) will starts the following procedure. ...
Page 33
... Power OFF flow with built-in power circuits USING PD BIT By setting PD=”H”, ST7577 will go into power save mode. The LCD driving outputs are all fixed to V circuits are turned OFF. After the built-in power circuits are turned OFF, the power (V Instruction Flow Note: 1 ...
Page 34
... ST7577 USING RESB Power OFF Flow <Start> (Sleep Out State) Set RESB=L Wait 250ms Turn Power OFF (VDD1 & VDD2) Power OFF Flow <End> (Sleep Out State) Instruction Flow Note Internal Power discharge time. => 250ms (max). OFF-RES 10 Period between VDD and VDD2 OFF time. => (max). ...
Page 35
... ST7577 12 Absolutely Maximum Rating In accordance with the Absolute Maximum Rating values; see notes 1 and 2. Parameter Digital Power Supply Voltage Analog Power supply voltage LCD Driver Power supply voltage Input voltage Operating temperature Storage temperature Notes 1. Stresses over the Absolutely Maximum Rating may cause permanent damage to the device. ...
Page 36
... ST7577 13. HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However totally safe desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices”). 14. DC CHARACTERISTICS Unless otherwise specified 2.4V to 3.3V Item Symbol Operation Voltage (1) ...
Page 37
... ST7577 Dynamic Current Consumption: During Display, with Internal Power Supply ON, current consumed by whole chip (bare die) Test pattern Symbol Display Pattern SNOW Booster X4 6.9 V; Bias=1/7; 1/39 Duty Power Down I SS Notes to the DC characteristics 1. The maximum V0 voltage may be generated will be limited ...
Page 38
... ST7577 15. TIMING CHARACTERISTICS System Bus Read/Write Characteristics (For the 8080 Series MPU) Item Address setup time Address hold time System cycle time /WR low pulse width /WR high pulse width /RD low pulse width /RD high pulse width WRITE Data setup time WRITE Data hold time ...
Page 39
... ST7577 System Bus Read/Write Characteristics (For the 6800 Series MPU) Item Address setup time Address hold time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time ...
Page 40
... ST7577 Serial Interface (4-Line Interface) Item Serial Clock Period SCL “H” pulse width SCL “L” pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time *1 The input signal rise and fall time (tr, tf) are specified less. ...
Page 41
... ST7577 Serial Interface (3-Line Interface) Item Serial Clock Period SCL “H” pulse width SCL “L” pulse width Data setup time Data hold time CS-SCL time CS-SCL time *1 The input signal rise and fall time (tr, tf) are specified less. ...
Page 42
... ST7577 Reset Timing Item Reset time Reset “L” pulse width Ver 1.0a Signal Symbol Condition t R RESB t RW 42/48 www.DataSheet4U.com V = 2.4~3.3V DD Rating Units Min. Typ. Max. μs 2.0 μs 2.0 2008/02/14 ...
Page 43
... ST7577 16. APPLICATION NOTE Selection of Application Voltage Power Range Summary l Positive Booster: (VDD2 x PCn x BE) ≥ (VDD2 x PCn x BE) ≥ Vop; l Negative Booster: [-VDD2 x (PCn - 1) x BE] ≤ XV0 or [VDD2 x (PCn -1) x BE] ≥ (Vop-VG), where VG = Vop Vop requirement: [VDD2 x (PCn - 1) x BE] ≥ [Vop x (N- Vop ≤ VDD2 x (PCn - (N-2). ...
Page 44
... ST7577 ITO Layout Reference (for Power) V0O V0S V0I Power Circuit Input, Output and Sensor ITO Layout (for V0, XV0 and VG ITO layout) IC Side ITO FPC R O V0O R I V0S R S V0I Equivalent Circuit Ver 1.0a VDD VDD2 Digital / Analog Power ITO Layout (Using Single Power) ...
Page 45
... /RW /RD CSB 132 SEG0 ~ SEG131 RESB ST7577 39 COM0 ~ COM38 R/W E CSB 132 SEG0 ~ SEG131 RESB ST7577 39 COM0 ~ COM38 SDA SCL A0 CSB 132 SEG0 ~ SEG131 RESB ST7577 39 COM0 ~ COM38 SDA SCL CSB 132 SEG0 ~ SEG131 RESB ST7577 45/48 www.DataSheet4U.com 2008/02/14 ...
Page 46
... ST7577 Application Circuits 8080 Interface (Port-A) 6800 Interface (Port-A) 6800 Interface PS2=“H” OSC=“H” Clock: Internal PS1=“H” MLB=“L” Data Format: LSB on Top PS0=“L” DTY=“L” Duty: 1/39 C1=0.1~1uF PM=“H” V0 Range: 4.5~8.31V C2=0.1~1uF MODE=“ ...
Page 47
... ST7577 Serial 4-Line SPI (Port-A) Serial 3-Line SPI (Port-A) Notes for all applications: l Recommend short noisy nets by FPC (refer to Page 43, ITO Layout). l The Microprocessor Interface pins should not be left floating under any operation mode. Ver 1.0a 47/48 www.DataSheet4U.com 2008/02/14 ...
Page 48
... ST7577 Reversion History Version l 0.0 Initial version l Modify Fig 12 0.1 l Modify application circuit. l Modify external power part. l Modify Power ON and OFF flow. 1.0 l Modify application circuit. l Update reference timing. l 1.0a Update date Ver 1.0a Description 48/48 www.DataSheet4U.com Date 2007/04/24 2007/07/24 2007/11/13 2008/02/14 2008/02/14 ...