TMP86FS49AFG Toshiba Semiconductor, TMP86FS49AFG Datasheet - Page 13

• Manufacturer Part Number: TMP86FS49AFG
• Description: 8-Bit Microcontroller
• Manufacturer: Toshiba Semiconductor

www.DataSheet4U.com
15. Synchronous Serial Interface (SIO2)
16. Serial Bus Interface(I2C Bus) Ver.-D (SBI)
17. 10-bit AD Converter (ADC)
15.1
15.2
15.3
16.1
16.2
16.3
16.4
16.5
16.6
17.1
14.3.3
15.3.1
15.3.2
15.3.3
16.5.1
16.5.2
16.5.3
16.5.4
16.5.5
16.5.6
16.5.7
16.5.8
16.5.9
16.5.10
16.5.11
16.5.12
16.5.13
16.6.1
16.6.2
16.6.3
16.6.4
16.6.5
14.3.2.2
14.3.2.3
14.3.3.1
14.3.3.2
14.3.3.3
15.3.1.1
15.3.1.2
15.3.2.1
15.3.2.2
15.3.2.3
15.3.3.1
15.3.3.2
15.3.3.3
16.5.1.1
16.5.1.2
16.5.3.1
16.5.3.2
16.6.3.1
16.6.3.2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
The Data Format in the I2C Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
I2C Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Data Transfer of I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Transfer modes................................................................................................................................... 165
Serial clock ......................................................................................................................................... 180
Transfer bit direction ........................................................................................................................... 182
Transfer modes................................................................................................................................... 183
Acknowledgement mode specification................................................................................................ 199
Number of transfer bits ....................................................................................................................... 200
Serial clock ......................................................................................................................................... 200
Slave address and address recognition mode specification ............................................................... 201
Master/slave selection ........................................................................................................................ 201
Transmitter/receiver selection............................................................................................................. 201
Start/stop condition generation ........................................................................................................... 202
Interrupt service request and cancel................................................................................................... 202
Setting of I2C bus mode ..................................................................................................................... 203
Device initialization ............................................................................................................................. 205
Start condition and slave address generation..................................................................................... 205
1-word data transfer............................................................................................................................ 205
Stop condition generation ................................................................................................................... 208
Restart ................................................................................................................................................ 209
Arbitration lost detection monitor ...................................................................................................... 203
Slave address match detection monitor............................................................................................ 204
GENERAL CALL detection monitor .................................................................................................. 204
Last received bit monitor................................................................................................................... 204
Receive mode
Transmit/receive mode
Transmit mode
Receive mode
Transmit/receive mode
Clock source
Shift edge
Transmit mode
Receive mode
Transmit/receive mode
Transmit mode
Receive mode
Transmit/receive mode
Acknowledgment mode (ACK = “1”)
Non-acknowledgment mode (ACK = “0”)
Clock source
Clock synchronization
When the MST is “1” (Master mode)
When the MST is “0” (Slave mode)
v