TMP86FS49AFG Toshiba Semiconductor, TMP86FS49AFG Datasheet - Page 217

• Manufacturer Part Number: TMP86FS49AFG
• Description: 8-Bit Microcontroller
• Manufacturer: Toshiba Semiconductor

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16.5.4 Slave address and address recognition mode specification
16.5.5 Master/slave selection
16.5.6 Transmitter/receiver selection
the ALS (Bit0 in I2CAR) to “0”, and set the SA (Bits7 to 1 in I2CAR) to the slave address.
ALS to “1”. With a free data format, the slave address and the direction bit are not recognized, and they are
processed as data from immediately after start condition.
should be cleared to “0”.
ware.
receiver, the TRX should be cleared to “0”. When data with an addressing format is transferred in the slave
mode, the TRX is set to "1" by a hardware if the direction bit (R/
cleared to “0” by a hardware if the bit is “0”. In the master mode, after an acknowledge signal is returned from
the slave device, the TRX is cleared to “0” by a hardware if a transmitted direction bit is “1”, and is set to "1"
by a hardware if it is “0”. When an acknowledge signal is not returned, the current condition is maintained.
When the serial bus interface circuit is used with an addressing format to recognize the slave address, clear
When the serial bus interface circuit is used with a free data format not to recognize the slave address, set the
To set a master device, the MST (Bit7 in SBICRB) should be set to “1”. To set a slave device, the MST
When a stop condition on the bus or an arbitration lost is detected, the MST is cleared to “0” by the hard-
To set the device as a transmitter, the TRX (Bit6 in SBICRB) should be set to "1". To set the device as a
SCL pin (Master 1)
SCL pin (Master 2)
SCL (Bus)
transfer even if there are two or more masters on the same bus.
bus.
low level. After detecting this situation, Master 2 resets counting a clock pulse in the high level and sets
the SCL pin to the low level.
level. Since Master 2 holds the SCL line of the bus at the low level, Master 1 waits for counting a clock
pulse in the high level. After Master 2 sets a clock pulse to the high level at point “c” and detects the SCL
line of the bus at the high level, Master 1 starts counting a clock pulse in the high level. Then, the master,
which has finished the counting a clock pulse in the high level, pulls down the SCL pin to the low level.
the master device with the longest low-level period from among those master devices connected to the
bus.
The serial bus interface circuit has a clock synchronization function. This function ensures normal
The example explains clock synchronization procedures when two masters simultaneously exist on a
As Master 1 pulls down the SCL pin to the low level at point “a”, the SCL line of the bus becomes the
Master 1 finishes counting a clock pulse in the low level at point “b” and sets the SCL pin to the high
The clock pulse on the bus is determined by the master device with the shortest high-level period and
Figure 16-4 Clock Synchronization
a
Count restart
Page 201
b
Wait
c
Count start
W
) sent from the master device is “1”, and is
Count reset
TMP86FS49AFG