TMP86FS49AFG Toshiba Semiconductor, TMP86FS49AFG Datasheet - Page 148

• Manufacturer Part Number: TMP86FS49AFG
• Description: 8-Bit Microcontroller
• Manufacturer: Toshiba Semiconductor

11.1 Configuration
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11.3.6 16-Bit Event Counter Mode (TC5 and 6)
11.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6)
TimerCounter 5 and 6 are cascadable to form the 16-bit PWM signal generator.
logic level output from the timer F/F6 is switched to the opposite state. The counter continues counting. The
logic level output from the timer F/F6 is switched to the opposite state again by the counter overflow, and the
counter is cleared. The INTTC6 interrupt is generated at this time.
mum frequency to be supplied is fc/2
or SLEEP1/2 mode.
generated. Upon reset, the timer F/F6 is cleared to 0.
PWREG6 and 5 can be changed while the timer is running. The values set to PWREG6 and 5 during a run of
the timer are shifted by the INTTCj interrupt request and loaded into PWREG6 and 5. While the timer is
stopped, the values are shifted immediately after the programming of PWREG6 and 5. Set the lower byte
(PWREG5) and upper byte (PWREG6) in this order to program PWREG6 and 5. (Programming only the lower
or upper byte of the register should not be attempted.)
read, but not the values set in PWREG6 and 5. Therefore, after writing to the PWREG6 and 5, reading data of
PWREG6 and 5 is previous value until INTTC6 is generated.
and 6 are cascadable to form a 16-bit event counter.
the timer is started by setting TC6CR<TC6S> to 1, an INTTC6 interrupt is generated and the up-counter is
cleared.
Two machine cycles are required for the low- or high-level pulse input to the TC5 pin.
2
order in the timer register. (Programming only the upper or lower byte should not be attempted.)
4
This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The
The counter counts up using the internal clock or external clock.
When a match between the up-counter and the timer register (PWREG5, PWREG6) value is detected, the
Two machine cycles are required for the high- or low-level pulse input to the TC5 pin. Therefore, a maxi-
Since the initial value can be set to the timer F/F6 by TC6CR<TFF6>, positive and negative pulses can be
(The logic level output from the
Since PWREG6 and 5 in the PWM mode are serially connected to the shift register, the values set to
If executing the read instruction to PWREG6 and 5 during PWM output, the values set in the shift register is
For the pin used for PWM output, the output latch of the I/O port must be set to 1.
Note 1: In the PWM mode, program the timer register PWREG6 and 5 immediately after the INTTC6 interrupt
Note 2: When the timer is stopped during PWM output, the
Note 1:
Note 2:
Note 3:
In the event counter mode, the up-counter counts up at the falling edge to the TC5 pin. The TimerCounter 5
When a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected after
After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TC5 pin.
Therefore, a maximum frequency to be supplied is fc/2
in the SLOW1/2 or SLEEP1/2 mode. Program the lower byte (TTREG5), and upper byte (TTREG6) in this
request is generated (normally in the INTTC6 interrupt service routine.) If the programming of PWREGj and
the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of
pulse different from the programmed value until the next INTTC6 interrupt request is generated.
stopped. To change the output status, program TC6CR<TFF6> after the timer is stopped. Do not program
TC6CR<TFF6> upon stopping of the timer.
Example: Fixing the
In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the
In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in
the shift register configuration in the event counter mode, the new value programmed in TTREGj is in effect imme-
diately after the programming. Therefore, if TTREGj is changed while the timer is running, an expected operation
may not be obtained.
j = 5, 6
PWM
6 pin to the high level when the TimerCounter is stopped
PWM
4
Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/2
6 pin is the opposite to the timer F/F6 logic level.)
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PWM
4
6 pin holds the output status when the timer is
Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/
PDOj
,
PWMj
and
PPGj
pins may output pulses.
4
TMP86FS49AFG
to in the SLOW1/2