UCC1810 Unitrode Semiconductor, UCC1810 Datasheet - Page 5

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UCC1810

Manufacturer Part Number
UCC1810
Description
Low Power BiCMOS Dual Current Mode PWM
Manufacturer
Unitrode Semiconductor
Datasheet
DETAILED BLOCK DIAGRAMS
LEADING EDGE BLANKING and CURRENT SENSE
OSCILLATOR
This diagram shows how an external power stage is connected to the UCC3810. The gate of an external power N-channel
MOSFET is connected to OUT through a small current limiting resistor. For most applications, a 10 resistor is adequate to limit
peak current and also practical at damping resonances between the gate driver and the MOSFET input reactance. Long gate
lead length increases gate capacitance and mandates a higher series gate resistor to damp the RLC tank formed by the lead,
the MOSFET input reactance, and the UCC3810 driver output resistance.
The UCC3810 features internal leading edge blanking of the current sense signal on both current sense inputs. The blank time
starts when OUT rises and continues for 55ns. During that 55ns period, the signal on CS is ignored. For most PWM applications,
this means that the CS input can be connected to the current sense resistor as shown above. However, high speed grounding
practices and short lead lengths are still required for good performance.
The UCC3810 oscillator generates a sawtooth wave at C
time is set by the resistor from R
rent in R
time is set by an internal transistor on-resistance of approximately 100 . Dur-
ing the fall time, all outputs are off and the maximum duty cycle is reduced be-
low 50%. Larger timing capacitors increase the discharge time and reduce
frequency. However, the percentage maximum duty cycle is only a function of
the timing resistor R
T
is 1V/R
T
. The actual charging current is 10 times higher. The fall
T
and the internal 100 discharge resistance.
T
to GND. Since R
T
is biased at 1V, the cur-
T
. The sawtooth rise
5
ERROR AMP OUTPUT STAGE
The UCC3810 error amplifiers are opera-
tional amplifiers with low output resistance
and high input resistance. The output stage
of one error amplifier is shown above. This
output stage allows the error amplifier out-
put to swing close to GND and as high as
one diode drop below 5V with little loss in
amplifier performance.
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