UCC1883 Unitrode Semiconductor, UCC1883 Datasheet - Page 6

• Manufacturer Part Number: UCC1883
• Description: Micropower Peak Current Mode Controller
• Manufacturer: Unitrode Semiconductor

APPLICATION INFORMATION (cont.)
9.5V LINEAR PRE-REGULATOR
The UCC1883 contains a control amplifier, which when
used with a depletion-mode NMOS pass transistor such
as the BSS129, can provide a 9.5V linear pre-regulator to
supply VCC directly from the input line. The depletion-
mode device guarantees the regulator is self-starting. By-
pass values less than 3.3 F are recommended when the
pre-regulator is utilized. The pre-regulator may sub-
sequently be fully disabled by a tertiary bootstrap winding
providing a minimum of 10.6V to the VCC pin. Note that
the UCC1883 has 2V of UVLO hysteresis to allow use of
more conventional startup circuitry, if the power
sumption of such implementations can be tolerated. In
these cases, any value of bypass capacitance is accept-
able, although a minimum value of 0.01 F is recom-
mended for all configurations.
INPUT CURRENT LIMIT PROGRAMMING
The UCC1883 also incorporates the necessary control
amplifier and current reference to implement a continuous
input current limit mask conforming to CCITT recommen-
dation I.430. When using this feature, the ratio of R
to R
by an external PMOS transistor. The PMOS device must
be able to withstand the maximum input voltage seen by
the converter, and its R
efficiency during normal operation, due to conduction
losses. Referencing the application diagram of Figure 7,
the control amplifier programs a peak input current ac-
cording to the equation
BIAS
Figure 5. Average DC Current vs. RBIAS (VCC = 12V) Not Including Power Switch Gate Current.
determines the magnitude of the current passed
ON
will cause some reduction in
SENSE
con-
6
by driving the gate of the external PMOS device until
equal voltage is impressed across RP and RS. In addition
to the input capacitance of the PMOS pass device, some
compensation capacitance from VLIMIT to VSS may be
required. However, too much capacitance on VLIMIT will
increase the inrush current response time beyond that al-
lowed by recommendation I.430. A total capacitance of
between 330pF and 2.2nF is recommended. A shunt
bleeder resistor should be added across the PMOS pass
transistor to facilitate converter startup. Due to the large
values of resistance which will typically be encountered,
a 10pF speedup capacitor across RP is suggested to
help maintain good phase margin in the control loop. A
clamping diode across RS improves transient response
by preventing excessive error voltage from being stored
on the RP speedup capacitor during VLIMIT slewing. Fi-
nally, a 12V zener clamp from VLIMIT to VSS is recom-
mended to protect the gate of the PMOS device from
over voltage and to limit the voltage slew which must oc-
cur before entering the current limit state. During normal
converter operation, when less than the programmed cur-
rent limit is being drawn from the line, the control loop
opens and VLIMIT moves to its maximum negative value,
effectively turning the PMOS limit transistor into a series
switch.
If a more accurate reference than that supplied by the
UCC1883 is desired, a precision resistor may be wired
from an appropriate reference voltage to IIN. Since IIN is
ILIMIT
RP
RS
1
RBIAS
0.4
UCC1883
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UDG-94085