UCC1883 Unitrode Semiconductor, UCC1883 Datasheet - Page 7

• Manufacturer Part Number: UCC1883
• Description: Micropower Peak Current Mode Controller
• Manufacturer: Unitrode Semiconductor

APPLICATION INFORMATION (cont.)
held at VSS (ground) by the current limit control amplifier,
the additional current created in this case is equal to the
reference voltage divided by the external resistor. A refer-
ence of at least 2V is recommended to eliminate errors
caused by the input offset voltage of the control amplifier.
Because the reference current provided by the UCC1883
sums into the IIN pin a minimum external reference cur-
rent value of 4V/RBIAS is recommended to minimize er-
rors caused by the initial tolerance of the internal current
reference.
FAULT HANDLING
Three fault conditions which immediately disable the out-
put are detected by the UCC1883 housekeeping circuitry.
These are:
Unlike the pulse-by-pulse current limit comparator, no
leading blanking is applied to the overcurrent fault com-
parator, which has a nominal 1.5V threshold. A capacitor
to VSS may be used on the COL pin to program the out-
put overload fault integrator. The polarity of the 2.2 A cur-
rent sourced by the internal circuitry driving the COL pin
potentially changes on each falling edge of OUT. If the
output pulse was terminated as the result of a peak cur-
rent event, then current is sourced to COL, otherwise cur-
rent is sunk from COL to VSS. If the voltage on COL ever
reaches 1.5V, a fault condition is set.
If any fault condition is detected once UVLO has ended,
the fault is latched and a restart delay elapses before a
soft start is attempted. This delay is normally controlled
by an internal 1 A discharge of the CSTART pin from
VDD to 0.2V. If a fault occurs during soft start, the output
1) UVLO,
2) 1.5V or higher on the ISENSE pin, and
3) 1.5V or higher on the COL integrator pin.
Figure 6. 9.5V Pre-regulator Application
7
is immediately disabled, but CSTART is fully charged
(4.8V) before a restart delay begins. A fixed restart delay
to soft start timing ratio of 25:1 may be obtained with only
a capacitor from CSTART to VSS. This ratio may be de-
creased by adding an external resistor between CSTART
and VSS. The value of this resistor should be greater
than the value of the current programming resistor on the
RBIAS pin.
ISOLATION INTERFACE
In addition to receiving synchronization and duty cycle
control information from the secondary side of the con-
verter, the UCC1883 isolation interface also transmits
digital status information to the secondary side. This digi-
tal information reflects the state of two internal analog
comparators which monitor the VLINE and IMODE pins.
A voltage of less than 1.2V on VLINE is indicated by a
true LOLINE bit, and an input current of less than 2 A
into the IMODE pin is interpreted as a true RSMODE (re-
stricted power mode) condition. These digital bits are
transmitted across the isolation barrier and appear as
outputs on the UCC1885 secondary-side regulation IC.
Recall that no UCC1885 output will occur until a voltage
greater than 1.2V is initially established on VLINE.
VDD LOGIC SUPPLY
The internal CMOS logic on the UCC1883 runs from a
regulated 5V which is available externally at the VDD pin.
This pin should be bypassed to VSS with a high quality
ceramic capacitor having a value of at least 0.01 F. Val-
ues in excess of 10 F are not recommended.
OSCILLATOR
A timing capacitor is connected between CT and VSS to
program a natural oscillator frequency according to the
equation
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