IDT72V3650 Integrated Device Technology, IDT72V3650 Datasheet - Page 42

• Manufacturer Part Number: IDT72V3650
• Description: 2k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

SYSTEM INTERFACE PARAMETERS
NOTE:
1. 50pf loading on external output signals.
TRST
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
Data Output Hold
TDI/
TMS
TDO
TCK
Data Output
Parameter
Data Input
t
DO
Symbol
t
3
t
DOH
t
t
= Max
DS
DH
t
5
(1)
Test Conditions
t
t
rise=3ns
t
fall=3ns
1
t
6
t
t
4
t
DS
TCK
Min.
10
10
t
0
-
DH
IDT72V3640
IDT72V3650
IDT72V3660
IDT72V3670
IDT72V3680
IDT72V3690
Figure 31. Standard JTAG Timing
Notes to diagram:
t1 = t
t2 = t
t3 = t
t4 = t
t5 = t
t6 = t
t
Max. Units
2
20
-
-
-
TCKHIGH
TCKFALL
TCKRise
RST
RSR
TCKLOW
(reset recovery)
(reset pulse width)
ns
ns
ns
TM
42
36-BIT FIFO
(V
NOTE:
1. Guaranteed by design.
JTAG AC ELECTRICAL
CHARACTERISTICS
JTAG Clock Input Period t
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
JTAG Reset Recovery
CC
= 3.3V
Parameter
±
5%; Tcase = 0°C to +85°C)
Symbol
t
t
t
t
t
t
TCK
TCKHIGH
TCKLOW
TCKRise
TCKFall
RST
RSR
COMMERCIAL AND INDUSTRIAL
Conditions Min. Max. Units
t
Test
DO
TEMPERATURE RANGES
-
-
-
-
-
-
-
100
40
40
50
50
-
-
APRIL 6, 2006
TDO
5
5
-
-
-
-
-
(1)
(1)
4667 drw36
ns
ns
ns
ns
ns
ns
ns