IDT72V3650 Integrated Device Technology, IDT72V3650 Datasheet - Page 7

• Manufacturer Part Number: IDT72V3650
• Description: 2k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

NOTE:
1. Inputs should not change state after Master Reset.
PIN DESCRIPTION-CONTINUED (TQFP & PBGA PACKAGES)
PIN DESCRIPTION (PBGA PACKAGE ONLY)
NOTE:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 42-45 and Figures 31-33.
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
SEN
WCLK/
WEN
V
ASYR
ASYW
TCK
TDI
TDO
TMS
TRST
WR
Symbol
Symbol
CC
(2)
(2)
(2)
(2)
(1)
(2)
(1)
Serial Enable
Write Clock/
Write Strobe
Write Enable
+3.3V Supply
Asynchronous
Read Port
Asynchronous
Write Port
JTAG Clock
JTAG Test Data
Input
JTAG Test Data
Output
JTAG Mode Select
JTAG Reset
Name
Name
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
SEN enables serial loading of programmable flag offsets.
If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK
writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into the FIFO
on a rising edge in an Asynchronous manner, (WEN should be tied to its active state). Asynchronous operation of
the WCLK/WR input is only available in the PBGA package.
WEN enables WCLK for writing data into the FIFO memory and offset registers.
These are V
A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.
A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
will select Asynchronous operation.
device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change
on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass Register.
An internal pull-up resistor forces TDI HIGH if left unconnected.
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass
Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through
its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically reset
upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP
controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG function is used
but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper FIFO operation. If the
JTAG function is not used then this signal needs to be tied to GND.
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the
CC
supply inputs and must be connected to the 3.3V supply rail.
TM
7
36-BIT FIFO
Description
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
APRIL 6, 2006