D68000 Digital Core Design, D68000 Datasheet - Page 3

• Manufacturer Part Number: D68000
• Description: 16/32-bit Microprocessor
• Manufacturer: Digital Core Design

Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implementa-
tion.
Unlimited Designs, One Year licenses allow use
IP Core in unlimited number of FPGA bit-
streams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restriction
except One Year license where time of use is
limited to 12 months.
●
●
●
●
ALU – Arithmetic Logic Unit performs the
arithmetic and logic operations during execution
of an instruction. It contains accumulator and
related logic such as arithmetic unit, logic unit,
multiplier and divider. BCD operation are exe-
cuted in this unit and condition code flags (N-
negative, Z-zero, C-carry V-overflow) for most
instructions.
Shifter – Performs shifting operations for the
appropriate instructions, mainly for rotation,
shift and bit operations.
All trademarks mentioned in this document
are trademarks of their respective owners.
○
○
○
○
○
○
○
Single Design license for
One Year license for
Unlimited Designs license for
Upgrade from
VHDL, Verilog source code called HDL Sour-
ce
Encrypted, or plain text EDIF called Netlist
Encrypted Netlist only
HDL Source
Netlist
HDL Source to Netlist
Single Design to Unlimited Designs
●
●
●
B L O C K D I A G R A M
Delivery the IP Core updates, minor
and major versions changes
Delivery the documentation updates
Phone & email support
L I C E N S I N G
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
Control Unit – Performs the core synchroniza-
tion and data flow control. This module man-
ages execution of all instructions. Contains SR
(status register is consisted of two portions su-
pervisor byte and user byte) and its related
logic.
Opcode Decoder – Performs an instruction
opcode decoding and the control functions for
all other blocks.
Memory Interface – Contains memory access
related registers It performs the memory ad-
dressing instructions code fetching and data
transfers. It is responsible for all external bus
cycle actions such as: read & write, repeated
read & write, halt and resume of bus cycles,
bus arbitration provided by 3- and 2- wire sys-
tem, correct bus and address errors handling,
wait states cycle insertion and M6800 synchro-
nous cycle generation.
Interrupt Controller – Interrupt Control module
is responsible for the interrupt manage system
for the external & internal interrupts and excep-
tions processing. It manages auto-vectored
interrupt cycles, priority resolving and correct
vector numbers creation.
Address registers – Contains 32-bit A0 to A6
address registers, two stack pointers USP (user
SP) and SSP (Supervisor SP), 32-bit Program
counter and related logic to perform word and
long address operations. An effective address
operation are executed in this unit.
Data registers – Contains 32-bit data registers
D0 to D7 and related logic to perform byte,
word and long data operations.
datao(15:0)
datai(15:0)
addr(23:0)
fc(2:0)
bgack
addrz
dataz
dtack
rdwr
vma
ctrlz
berr
epd
uds
vpa
lds
clk
bg
as
br
http://www.DigitalCoreDesign.com
http://www.dcd.pl
registers
registers
interface
Address
Memory
Data
controller
decoder
Interrupt
Opcode
Control
Shifter
ALU
unit
ipl(2:0)
rsto
rsti
halti
halto