dq8051xp Digital Core Design, dq8051xp Datasheet
dq8051xp
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dq8051xp Summary of contents
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... This ratio is extended by an advanced power man‐ agement unit PMU. DQ8051XP soft core is 100% binary‐ compatible with the industry standard 8051 8‐bit microcontroller. DQ8051 has build‐in configurable ...
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... Area utilized by the each unit of DQ8051XP core in vendor specific technologies is summarized in table below. ...
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Program Memory ○ Internal (direct) Data Memory ○ Special Function Registers (SFRs) ○ External Data Memory ○ Code execution breakpoints ○ two real‐time PC breakpoint ○ unlimited number of real‐time OPCODE breakpoints ○ Hardware execution watch‐points at ○ Internal (direct) Data Memory ○ Special Function Registers (SFRs) ○ External Data Memory ○ Hardware watch‐points activated at a certain ○ address by any write into memory ○ address by any read from memory ○ address by write into memory a required data ○ address by read from memory a required data ○ Automatic adjustment of debug data transfer speed rate between HAD and Silicon ○ JTAG Communication interface ● Power Management Unit ...
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... And more peripherals The following parameters of the DQ8051XP core can be easy adjusted to requirements of dedi‐ cated application and technology. Configuration of the core can be prepared by effortless changing ...
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... The DQ8051XP soft core can address up to 64 kB of fast on‐chip Synchronous External Data Memory. All reads and writes are exe‐ ...
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Opcode I/O Port decoder registers prgaddr prgdatao Program prgdatai Timers memory prgdataz prgrdy interface prgrd prgwr xaddress Interrupt xdatao External xdatai controller data xdataz memory xdatardy ...
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PIN TYPE DESCRIPTION rsto output Reset output port0o output Port 0 output port1o output Port 1 output port2o output Port 2 output port3o output Port 3 output prgaddr output Internal program memory address bus prgdatao output Data bus for internal program memory prgdataz output Turn prgdata bus into ‘Z’ state prgwr output Program memory write prgrd output Program memory read Synchronous XDATA memory address sxdmaddr output bus Data bus for Synchronous XDATA sxdmdatao ...
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Internal Data Memory Interface – Internal Data Memory interface controls access into the internal 256 bytes memory. It contains 8‐bit Stack Pointer (SP) register and related logic. User SFRs Interface – Special Function Registers interface controls access to the special registers. It contains standard and used defined ...
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T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs. Timer 2 – Second system timer module contains one 16‐bit configurable timer: Timer 2 ...
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SPI devices simultane‐ ously attempts to become bus master. All trademarks mentioned in this document are trademarks of their respective owners. Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved ...
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... DQ8051 25.1 64k 64k 64k 256 256 DQ8051XP 26.6 64k 64k 64k 256 256 DQ8051 family of Pipelined High Performance Microcontroller Cores ...