DZ80 Digital Core Design, DZ80 Datasheet - Page 2

• Manufacturer Part Number: DZ80
• Description: 8-bit Microprocessor
• Manufacturer: Digital Core Design

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major versions changes
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L I C E N S I N G
Copyright 1999-2006 DCD – Digital Core Design. All Rights Reserved.
clk
rst
int
nmi
wait
busreq
datai[7:0]
datao[7:0]
addr[15:0]
wr
rd
busack
m1
mreq
iorq
rfsh
halt
Control Unit - Performs the core synchroniza-
tion and data flow control. This module man-
ages execution of all instructions. The Control
Unit also manages execution of HALT state and
waking-up the processor from the HALT mode.
Opcode Decoder - Performs an instruction
opcode decoding and the control functions for
all other blocks.
PIN
P I N S D E S C R I P T I O N
B L O C K D I A G R A M
datai(7:0)
int
nmi
busrq
wait
clk
rst
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ACTIVE
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
-
-
-
-
S Y M B O L
output
output
output
output
output
output
output
output
output
output
TYPE
input
input
input
input
input
input
input
Global system clock
Global reset input
Interrupt request
Non-Maskable Interrupt Request
WAIT input
Bus Request
Memory bus input
Data memory & UFR bus output
Write enable
Read enable
Bus Acknowledge
Machine Cycle One
Memory Request
Input/Output Request
Refresh
Halt State
Data memory address bus
addr(15:0)
datao(7:0)
busack
DESCRIPTION
mreq
halt
iorq
rfsh
m1
wr
rd