HT46R48E Holtek Semiconductor, HT46R48E Datasheet
HT46R48E
Related parts for HT46R48E
HT46R48E Summary of contents
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... A/D applications that interface directly to analog sig- nals, such as those from sensors. There are two dice in the HT46R48E package: one is the HT46R48 MCU, the other is a 128 8 bits EEPROM used for data memory purpose. The two dice are wire-bonded to form HT46R48E ...
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... Block Diagram Data EEPROM Rev. 1.10 2 HT46R48E March 24, 2006 ...
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... Negative power supply, ground. OSC1, OSC2 are connected network or a Crystal (determined by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... HT46R48E March 24, 2006 ...
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... HALT load, system HALT 0.9V DD 2.7 V =0. =0. =0. =0. HT46R48E Ta=25 C Typ. Max. Unit 5.5 V 5.5 V 0.6 1 0.8 1 ...
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... CC 2. f=1MHz 25 C f=1MHz 25 C Test Conditions Min. V Conditions DD 2.2V~5.5V 400 3.3V~5.5V 400 2.2V~5.5V 0 3.3V~5. Wake-up from HALT 0. HT46R48E Ta=25 C Typ. Max. Unit Ta=25 C Typ. Max. Unit ...
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... Only relevant for repeated 4000 START condition 0 200 4000 3500 Time in which the bus must be free before a new trans- 4700 mission can start Noise suppression time =2.2V to 5.5V 6 HT46R48E Ta= =5V 10% CC Unit Min. Max. 100 400 kHz 600 ns 1200 ns ...
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... Program Counter Program Counter S10~S0: Stack register bits @7~@0: PCL bits 7 HT46R48E * ...
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... At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the pro- gram counter is restored to its previous value from the Table Location * Table Location P10~P8: Current program counter bits 8 HT46R48E * March 24, 2006 ...
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... This circuit performs 8-bit arithmetic and logic opera- tions. The ALU provides the following functions: Arithmetic operations (ADD, ADC, SUB, SBC, DAA) Logic operations (AND, OR, XOR, CPL) Rotation (RL, RR, RLC, RRC) Increment and Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ, SDZ ....) 9 HT46R48E March 24, 2006 ...
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... INTC), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF bit is set, a subroutine call to location 08H will occur. The re- lated interrupt request flag (TF) will be reset and the EMI bit cleared to disable further interrupts. Function Status (0AH) Register 10 HT46R48E March 24, 2006 ...
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... How- ever, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process varia- tions. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. 11 HT46R48E March 24, 2006 ...
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... If the interrupt is enabled and the stack is not full, the regu- lar interrupt response takes place interrupt request CLR flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Watchdog Timer 12 HT46R48E March 24, 2006 ...
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... Timer/Event Counter Off Input/Output Ports Input mode Stack Pointer Points to the top of the stack Reset Circuit Note: * Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference. Reset Timing Chart Reset Configuration 13 HT46R48E March 24, 2006 ...
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... TMR returns to the orig- inal level and resets the TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only one cycle 14 HT46R48E RES Reset WDT Times-out (HALT) (HALT)* ...
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... The definitions are as shown. The overflow signal of timer/event counter can be used to generate the PFD signal. Function SYS /2 SYS /4 SYS /8 SYS /16 SYS /32 SYS /64 SYS /128 SYS TMRC (0EH) Register Timer/Event Counter 15 HT46R48E March 24, 2006 ...
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... PFD output function and writing 0 will force the PA3 to remain The I/O functions of PA3 are shown below. I/O I/P O/P Mode (Normal) (Normal) Logical Logical PA3 Input Output Note: The PFD frequency is the timer/event counter overflowfrequencydividedby 2. Input/Output Ports 16 HT46R48E I/P O/P (PFD) (PFD) Logical PFD Input (Timer on) March 24, 2006 ...
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... ADRL (20H), ADRH (21H), ADCR (22H) and ACSR (23H). The ADRH and ADRL are A/D result register higher-order byte and lower-order byte and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be read to get the conversion PWM 17 HT46R48E Duty Cycle DC+1 i< ...
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... Port B channel selec- tion bits being modified. Note that if the Port B channel selection bits are all cleared to zero then an A/D initial- ization is not required. Bit5 Bit4 Bit3 ADRL (20H), ADRH (21H) Register Function ADCR (22H) Register 18 HT46R48E Bit2 Bit1 Bit0 March 24, 2006 ...
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... As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START ; reset A/D clr START ; start A/D clr ADF ; clear ADC interrupt request flag Rev. 1.10 Function ACSR (23H) Register /8 as the A/D clock SYS /8 as the A/D clock SYS 19 HT46R48E March 24, 2006 ...
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... START set START ; reset A/D clr START ; start A EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 1.10 A/D Conversion Timing 20 HT46R48E March 24, 2006 ...
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... PFD enable or disable 9 Low voltage reset selection: enable or disable LVR function. Rev. 1.10 The relationship between V Note the voltage range for proper chip OPR operation at 4MHz system clock. Low Voltage Reset Options TID 21 HT46R48E and V is shown below. DD LVR March 24, 2006 ...
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... If the device is still busy imple- menting its write cycle, then no ACK will be returned. The master can send the next read/write command when the ACK signal has finally been received. Byte Write Timing 22 HT46R48E March 24, 2006 ...
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... The sequential read operation is terminated when the microcontroller responds with a no ACK sig- nal (high) followed by a stop condition. Current Read Timing Random Read Timing Sequential Read Timing 23 HT46R48E March 24, 2006 ...
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... Data EEPROM Timing Diagrams Note: The write cycle time t is the time from a valid stop condition of a write sequence to the end of the valid start WR condition of sequential command. Rev. 1.10 24 HT46R48E March 24, 2006 ...
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... RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.10 C1 0pF 10k 10pF 12k 0pF 10k 25pF 10k 25pF 10k 35pF 27k 300pF 9.1k 300pF 10k 300pF 10k 25 HT46R48E March 24, 2006 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.10 Description 26 HT46R48E Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.10 Description 27 HT46R48E Instruction Flag Cycle Affected 2 None (2) 1 None ...
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... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.10 PDF PDF PDF PDF PDF HT46R48E March 24, 2006 ...
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... Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.10 PDF PDF PDF addr PDF PDF HT46R48E March 24, 2006 ...
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... Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.10 PDF PDF PDF PDF PDF HT46R48E March 24, 2006 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.10 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C PDF PDF PDF HT46R48E March 24, 2006 ...
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... Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.10 Program Counter+1 PDF PDF PDF addr PDF PDF HT46R48E March 24, 2006 ...
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... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.10 PDF PDF Program Counter+1 PDF PDF PDF PDF HT46R48E March 24, 2006 ...
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... Affected flag(s) TO ¾ Rev. 1.10 PDF ¾ ¾ ¾ ¾ PDF ¾ ¾ ¾ ¾ PDF ¾ ¾ ¾ ¾ PDF ¾ ¾ ¾ ¾ PDF ¾ ¾ ¾ ¾ 34 HT46R48E C ¾ C ¾ C ¾ C ¾ C ¾ March 24, 2006 ...
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... Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.10 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF PDF PDF HT46R48E March 24, 2006 ...
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... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.10 PDF PDF PDF ([m] 1) PDF ([m] 1) PDF HT46R48E March 24, 2006 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.10 PDF PDF ([m]+1) PDF ([m]+1) PDF PDF HT46R48E March 24, 2006 ...
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... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.10 PDF PDF PDF [m].7~[m].4 PDF [m].7~[m].4 [m].3~[m].0 PDF HT46R48E March 24, 2006 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.10 PDF PDF PDF PDF PDF HT46R48E March 24, 2006 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.10 PDF PDF PDF HT46R48E March 24, 2006 ...
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... Package Information 24-pin SKDIP (300mil) Outline Dimensions Symbol Rev. 1.10 Dimensions in mil Min. Nom. 1235 255 125 125 16 50 100 295 345 0 41 HT46R48E Max. 1265 265 135 145 20 70 315 360 15 March 24, 2006 ...
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... SOP (300mil) Outline Dimensions Symbol Rev. 1.10 Dimensions in mil Min. Nom. 394 290 14 590 HT46R48E Max. 419 300 20 614 104 March 24, 2006 ...
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... SSOP (150mil) Outline Dimensions Symbol Rev. 1.10 Dimensions in mil Min. Nom. 228 150 8 335 HT46R48E Max. 244 157 12 346 March 24, 2006 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 24S (150mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.10 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 24.8+0.3 0.2 30.2 0.2 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 16.8+0.3 0.2 22.2 0.2 44 HT46R48E March 24, 2006 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.10 Dimensions in mm 24.0 0.3 12.0 0.1 1.75 0.1 11.5 0.1 1.55+0.1 1.5+0.25 4.0 0.1 2.0 0.1 10.9 0.1 15.9 0.1 3.1 0.1 0.35 0.05 21.3 Dimensions in mm 16.0+0.3 0.1 8.0 0.1 1.75 0.1 7.5 0.1 1.5+0.1 1.5+0.25 4.0 0.1 2.0 0.1 6.5 0.1 9.5 0.1 2.1 0.1 0.3 0.05 13.3 45 HT46R48E March 24, 2006 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 46 HT46R48E March 24, 2006 ...