HT46R48E Holtek Semiconductor, HT46R48E Datasheet - Page 18

• Manufacturer Part Number: HT46R48E
• Description: Cost-Effective A/D Type 8-Bit OTP MCU
• Manufacturer: Holtek Semiconductor

result data. The ADCR is an A/D converter control regis-
ter, which defines the A/D channel number, analog
channel select, start A/D conversion control bit and the
end of A/D conversion flag. If the users want to start an
A/D conversion, define PB configuration, select the con-
verted analog channel, and give START bit a raising
edge and a falling edge (0 1 0). At the end of A/D
conversion, the EOCB bit is cleared and an A/D con-
verter interrupt occurs (if the A/D converter interrupt is
enabled). The ACSR is A/D clock setting register, which
is used to select the A/D clock source.
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There are a total of four
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled, and the
A/D converter circuit is power on. The EOCB bit (bit6 of
the ADCR) is end of A/D conversion flag. Check this bit
to know when A/D conversion is completed. The START
bit of the ADCR is used to begin the conversion of A/D
Note:
Rev. 1.10
Bit No.
ADRH (21H)
ADRL (20H)
Register
0
1
2
3
4
5
6
7
D0~D8 is A/D conversion result data bit LSB~MSB.
START
EOCB
Label
ACS0
ACS1
ACS2
PCR0
PCR1
PCR2
Bit7
D0
D8
ACS2, ACS1, ACS0: Select A/D channel
0, 0, 0: AN0
0, 0, 1: AN1
0, 1, 0: AN2
0, 1, 1: AN3
1, X, X: undefined, cannot be used
PCR2, PCR1, PCR0: PB3~PB0 configurations
0, 0, 0: PB3 PB2 PB1 PB0 (The ADC circuit is power off to reduce power consump-
tion.)
0, 0, 1: PB3 PB2 PB1 AN0
0, 1, 0: PB3 PB2 AN1 AN0
0, 1, 1: PB3 AN2 AN1 AN0
1, x, x: AN3 AN2 AN1 AN0
Indicates end of A/D conversion. (0 = end of A/D conversion)
Each time bits 3~5 change state the A/D should be initialized by issuing a START sig-
nal, otherwise the EOCB flag may have an undefined condition. See Important note
for A/D initialization .
Start the A/D conversion
0 1 0= Start
0 1= Reset A/D converter and set EOCB to 1
Bit6
D7
ADRL (20H), ADRH (21H) Register
ADCR (22H) Register
Bit5
D6
18
Bit4
D5
converter. Give START bit a raising edge and falling
edge that means the A/D conversion has started. In or-
der to ensure the A/D conversion is completed, the
START should stay at 0 until the EOCB is cleared to
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the applica-
tion program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
When the A/D conversion has completed, the A/D inter-
rupt request flag will be set. The EOCB bit is set to 1
when the START bit is set from 0 to 1 .
Important Note for A/D initialization:
Special care must be taken to initialize the A/D con-
verter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an un-
defined condition. An A/D initialization is implemented
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selec-
tion bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initial-
ization is not required.
0 (end of A/D conversion).
Function
Bit3
D4
Bit2
D3
Bit1
D2
HT46R48E
March 24, 2006
Bit0
D1