PDSP16116MC Zarlink Semiconductor, PDSP16116MC Datasheet - Page 13

• Manufacturer Part Number: PDSP16116MC
• Description: 16 by 16 Bit Complex Multiplier
• Manufacturer: Zarlink Semiconductor

The butterfly operation
repeated many times to produce an FFT. The PDSP16116A
based butterfly processor performs this operation in a low
power high accuracy chip set.
The butterfly operation is the arithmetic operation which is
Output A'r, A'i, B'r, B'i
Output DAr, DAi
Wr, Wi to inputs
Output WTOUT
Present Br, Bi,
WTB to inputs
Present WTA,
Output SFTR
Output SFTA
Output Pr, Pi
Present Ar,
A
B
Ai to inputs
Figure 6 - Butterfly Operation
CLK
W
n-2
n-3
n-2
n-3
n-5
n-5
n
n
n
A' = A + B. W
B' = A - B. W
A'
B'
Figre 7 Butterfly Data and Control Signals
n+1
n+1
n+1
n-1
n-2
n-1
n-2
n-4
n-4
n+2
n+2
n+2
n-1
n-1
n-1
n-3
n-3
n
requiring a new set of data for , B, W, WTA and WTB. Five
cycles later, the corresponding results A' and B' are produced
along with their associated WTOUT. In between, the signals
SFTA and SFTR are produced and acted upon by the shifters
in the PDSP1601/A and PDSP16318/A. The timing of the data
and control signals is shown in Fig.6.
pass must be stored away to be used later as the input data
(A and B) in the next pass. Each result must be stored together
with its associated word tag, WTOUT. Although WTOUT is
common to both A' and B', it must be stored separately with
each word as the words are used on different cycles during the
next pass. At the inputs, the word tag associated with the A
word is known as WTA and the word tag associated with the
B word is known as WTB. Hence, the WTOUTs from one pass
will become the WTAs and WTBs for the following pass. It
should be noted that the first pass is unique in that word tags
need not be input into the butterfly as all data initially has the
same weighting. Hence, during the first pass alone, the inputs
WTA and WTB are ignored.
A new butterfly operation is commenced each cycle,
The results (A' and B') of each butterfly calculation in a
n+3
n+3
n+3
n+1
n-2
n-2
n
n
n
n+4
n+4
n+4
n+2
n+1
n+1
n+1
n-1
n-1
PDSP16116/A/MC
n+5
n+5
n+5
n+3
n+2
n+2
n+2
n
n
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